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Add MCP feature to Pipeline-C

enhancementNew feature or requestNew feature or request

Status: Open.

#18 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Jun 5, 2025

Add our ALINX AX7201 card to LiteX

task

Status: Open.

#15 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Feb 27, 2025

Verilator linting of AXIS and Ethernet libs fails

lintRTL Linting issuesRTL Linting issues

Status: Open.

#14 In chili-chips-ba/wireguard-fpga;

· eniokaljic opened on Feb 25, 2025

Add ability for interactive control of sim execution

Status: Open.

#11 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Dec 2, 2024

Creation of automated CSR test for RISC-V, based on RDL register definition

discussion

Status: Open.

#10 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Nov 24, 2024

Header Parser and IP Lookup function

discussion

Status: Open.

#6 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Nov 15, 2024

Timing-aware ISS model

discussion

Status: Open.

#3 In chili-chips-ba/wireguard-fpga;

· chili-chips-ba opened on Nov 10, 2024