Quartus reset-n fix #1826
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Quartus reset-n fix #1826
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Quartus detects reset polarity from the signal role, and inserts adapaters automatically. The IP affected by this commit were previously assigning the wrong (active high) polarity to active-low resets. This can cause multiple problems. The i3c controller and spi engine resets are generated by other IPs in the framework, and these were also detected as wrong polarity, hence it being undetected so far. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
ad4170_asdz and ad469x_evb both used some logic at the top level to synchronize a signal from the ADC to the SPI Engine domain, and then to detect a falling edge on the synchronized signal, using it as a trigger for the SPI Engine. Recently, the SPI Engine was updated to use an edge-based trigger, with the appropriate synchronizer logic added, so this extra logic is no longer needed. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
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dlech
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Jul 7, 2025
| @@ -32,7 +32,6 @@ proc p_elaboration {} { | |||
| # control interface | |||
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| ad_interface clock ctrl_clk input 1 | |||
| ad_interface reset spi_resetn input 1 if_spi_clk | |||
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Why is this one deleted instead of replaced?
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Because it's defined twice on the file.
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PR Description
Fixes reset polarity on
util_sigma_delta_spi, SPI Engine and I3C Controller IPs on Quartus.Quartus inserts adapters between reset polarities automatically, based on how each reset interface is defined on the block design.
This went by undetected so far because in most use cases the affected IPs had their resets generated by other affected IPs (so it was detecting as the wrong polarity on both the output and input, cancelling out).
This was causing issues on
ad411x_ad717x/de10nanobecause theutil_sigma_delta_spiIP would be permanently reset and never trigger. It could have caused issues for other Quartus projects which use eitherutil_sigma_delta_spi, or any of the SPI Engine or I3C Controller framework IPs as long as their reset would come from an unaffected IP.The second commit cleans up some extra logic on the top level for
ad4170_asdz/de10nanoandad469x_evb/de10nano, which was used to synchronize and detect the falling edge of an ADC signal for use as the SPI Engine trigger, but is no longer need since this logic is now present in the SPI Engine.PR Type
PR Checklist