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projects/ad4170; projects/ad469x_evb: simplify unneeded logic
ad4170_asdz and ad469x_evb both used some logic at the top level to synchronize a signal from the ADC to the SPI Engine domain, and then to detect a falling edge on the synchronized signal, using it as a trigger for the SPI Engine. Recently, the SPI Engine was updated to use an edge-based trigger, with the appropriate synchronizer logic added, so this extra logic is no longer needed. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
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-84
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4 files changed

+5
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‎projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -35,18 +35,6 @@ add_instance spi_engine_interconnect_0 spi_engine_interconnect
3535
set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
3636
set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
3737

38-
# bridges
39-
40-
add_instance clock_bridge_0 altera_clock_bridge
41-
set_instance_parameter_value clock_bridge_0 {EXPLICIT_CLOCK_RATE} {0.0}
42-
set_instance_parameter_value clock_bridge_0 {NUM_CLOCK_OUTPUTS} {1}
43-
44-
add_instance reset_bridge_0 altera_reset_bridge
45-
set_instance_parameter_value reset_bridge_0 {ACTIVE_LOW_RESET} {1}
46-
set_instance_parameter_value reset_bridge_0 {NUM_RESET_OUTPUTS} {1}
47-
set_instance_parameter_value reset_bridge_0 {SYNCHRONOUS_EDGES} {none}
48-
set_instance_parameter_value reset_bridge_0 {USE_RESET_REQUEST} {0}
49-
5038
# spi_engine_offload
5139

5240
add_instance spi_engine_offload_0 spi_engine_offload
@@ -62,22 +50,15 @@ add_interface ad4170_spi_cs conduit end
6250
add_interface ad4170_spi_sdi conduit end
6351
add_interface ad4170_spi_sdo conduit end
6452
add_interface ad4170_spi_trigger conduit end
65-
add_interface ad4170_spi_resetn reset source
6653

6754
set_interface_property ad4170_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
6855
set_interface_property ad4170_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
6956
set_interface_property ad4170_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
7057
set_interface_property ad4170_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
7158
set_interface_property ad4170_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
72-
set_interface_property ad4170_spi_resetn EXPORT_OF reset_bridge_0.out_reset
73-
74-
add_connection axi_spi_engine_0.if_spi_resetn reset_bridge_0.in_reset
7559

7660
# clocks
7761

78-
add_interface ad4170_spi_clk clock source
79-
set_interface_property ad4170_spi_clk EXPORT_OF clock_bridge_0.out_clk
80-
8162
add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
8263
add_connection sys_clk.clk axi_dmac_0.s_axi_clock
8364

@@ -88,7 +69,6 @@ add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
8869
add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
8970
add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
9071
add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
91-
add_connection sys_dma_clk.clk clock_bridge_0.in_clk
9272

9373
# resets
9474

‎projects/ad4170_asdz/de10nano/system_top.v

Lines changed: 3 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -147,9 +147,6 @@ module system_top (
147147
wire i2c0_scl_in_clk;
148148

149149
wire spi_trigger;
150-
wire spi_clk_s;
151-
wire spi_resetn;
152-
wire spi_trigger_ed;
153150

154151
// adc control gpio assign
155152

@@ -160,6 +157,8 @@ module system_top (
160157

161158
assign gpio_i[33:32] = ad4170_dig_aux[1:0];
162159

160+
assign spi_trigger = ~gpio_i[32];
161+
163162
// bd gpio
164163

165164
assign gpio_i[13:8] = gpio_bd_i[5:0];
@@ -191,22 +190,6 @@ module system_top (
191190
.o(i2c0_sda),
192191
.io(hdmi_i2c_sda));
193192

194-
sync_bits #(
195-
.ASYNC_CLK(1)
196-
) i_sync_bits (
197-
.in_bits (gpio_i[32]),
198-
.out_resetn (~spi_resetn),
199-
.out_clk (spi_clk_s),
200-
.out_bits (spi_trigger_ed));
201-
202-
ad_edge_detect#(
203-
.EDGE(1)
204-
) i_ad_edge_detect (
205-
.clk (spi_clk_s),
206-
.rst (1'b0),
207-
.signal_in (spi_trigger_ed),
208-
.signal_out (spi_trigger));
209-
210193
system_bd i_system_bd (
211194
.sys_clk_clk (sys_clk),
212195
.sys_hps_h2f_reset_reset_n (sys_resetn),
@@ -283,8 +266,6 @@ module system_top (
283266
.ad4170_spi_sdi_sdi (ad4170_spi_miso),
284267
.ad4170_spi_sdo_sdo (ad4170_spi_mosi),
285268
.ad4170_spi_trigger_if_pwm (spi_trigger),
286-
.ad4170_spi_resetn_reset_n (spi_resetn),
287-
.ad4170_spi_clk_clk (spi_clk_s),
288269
.sys_spi_MISO (1'b0),
289270
.sys_spi_MOSI (),
290271
.sys_spi_SCLK (),

‎projects/ad469x_evb/common/ad469x_qsys.tcl

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -35,18 +35,6 @@ add_instance spi_engine_interconnect_0 spi_engine_interconnect
3535
set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
3636
set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
3737

38-
# bridges
39-
40-
add_instance clock_bridge_0 altera_clock_bridge
41-
set_instance_parameter_value clock_bridge_0 {EXPLICIT_CLOCK_RATE} {0.0}
42-
set_instance_parameter_value clock_bridge_0 {NUM_CLOCK_OUTPUTS} {1}
43-
44-
add_instance reset_bridge_0 altera_reset_bridge
45-
set_instance_parameter_value reset_bridge_0 {ACTIVE_LOW_RESET} {1}
46-
set_instance_parameter_value reset_bridge_0 {NUM_RESET_OUTPUTS} {1}
47-
set_instance_parameter_value reset_bridge_0 {SYNCHRONOUS_EDGES} {none}
48-
set_instance_parameter_value reset_bridge_0 {USE_RESET_REQUEST} {0}
49-
5038
# spi_engine_offload
5139

5240
add_instance spi_engine_offload_0 spi_engine_offload
@@ -111,24 +99,16 @@ add_interface ad469x_spi_sdi conduit end
11199
add_interface ad469x_spi_sdo conduit end
112100
add_interface ad469x_spi_trigger conduit end
113101
add_interface ad469x_spi_cnv conduit end
114-
add_interface ad469x_spi_resetn reset source
115102

116103
set_interface_property ad469x_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
117104
set_interface_property ad469x_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
118105
set_interface_property ad469x_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
119106
set_interface_property ad469x_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
120107
set_interface_property ad469x_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
121108
set_interface_property ad469x_spi_cnv EXPORT_OF ad469x_trigger_gen.if_pwm_0
122-
set_interface_property ad469x_spi_resetn EXPORT_OF reset_bridge_0.out_reset
123-
124-
add_connection axi_spi_engine_0.if_spi_resetn reset_bridge_0.in_reset
125109

126110
# clocks
127111

128-
add_interface ad469x_spi_clk clock source
129-
set_interface_property ad469x_spi_clk EXPORT_OF clock_bridge_0.out_clk
130-
131-
132112
add_connection sys_clk.clk spi_clk_pll.refclk
133113
add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
134114
add_connection sys_clk.clk ad469x_trigger_gen.s_axi_clock

‎projects/ad469x_evb/de10nano/system_top.v

Lines changed: 2 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -156,14 +156,12 @@ module system_top #(
156156
wire ad469x_spi_cs_s;
157157

158158
wire spi_trigger;
159-
wire spi_clk_s;
160-
wire spi_resetn;
161-
wire spi_trigger_ed;
162159
wire dma_xfer_req;
163160

164161
assign ad469x_spi_cnv = (SPI_4WIRE == 0) ? ad469x_spi_cnv_s : ad469x_spi_cs_s;
165162
assign ad469x_spi_cs = ad469x_spi_cs_s;
166163
assign ad469x_spi_cnv_s = (spi_pwm & dma_xfer_req) | gpio_o[35];
164+
assign spi_trigger = ~ad469x_busy_alt_gp0;
167165

168166
// adc control gpio assign
169167

@@ -206,22 +204,6 @@ module system_top #(
206204
.o(i2c0_sda),
207205
.io(hdmi_i2c_sda));
208206

209-
sync_bits #(
210-
.ASYNC_CLK(1)
211-
) i_sync_bits (
212-
.in_bits (ad469x_busy_alt_gp0),
213-
.out_resetn (~spi_resetn),
214-
.out_clk (spi_clk_s),
215-
.out_bits (spi_trigger_ed));
216-
217-
ad_edge_detect#(
218-
.EDGE(1)
219-
) i_ad_edge_detect (
220-
.clk (spi_clk_s),
221-
.rst (1'b0),
222-
.signal_in (spi_trigger_ed),
223-
.signal_out (spi_trigger));
224-
225207
system_bd i_system_bd (
226208
.sys_clk_clk (sys_clk),
227209
.sys_hps_h2f_reset_reset_n (sys_resetn),
@@ -297,8 +279,6 @@ module system_top #(
297279
.ad469x_spi_sclk_clk (ad469x_spi_sclk),
298280
.ad469x_spi_sdi_sdi (ad469x_spi_sdi),
299281
.ad469x_spi_sdo_sdo (ad469x_spi_sdo),
300-
.ad469x_spi_resetn_reset_n (spi_resetn),
301-
.ad469x_spi_clk_clk (spi_clk_s),
302282
.ad469x_spi_cnv_if_pwm (spi_pwm),
303283
.ad469x_spi_trigger_if_pwm(spi_trigger),
304284
.dma_xfer_req_xfer_req(dma_xfer_req),

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