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Add programming guide section with common IRON errors

Status: Open.

#2594 In Xilinx/mlir-aie;

· AndraBisca opened on Sep 18, 2025

· 

IRON Release XXX

Enable aie_kernel_utils.h include

Status: Open.

#2593 In Xilinx/mlir-aie;

· AndraBisca opened on Sep 18, 2025

· 

IRON Release 1.2.0

Add whole-array Softmax getting-started example

Status: Open.

#2592 In Xilinx/mlir-aie;

· AndraBisca opened on Sep 18, 2025

· 

IRON Release 1.2.0

Extend ObjectFifo packet-switched lowering to Mem tiles

Status: Open.

#2591 In Xilinx/mlir-aie;

· AndraBisca opened on Sep 18, 2025

· 

IRON Release 1.2.0

Problem Implementing Broadcast with skip objectfifo for GRU network

Status: Open.

#2586 In Xilinx/mlir-aie;

· iuwizeyimana opened on Sep 17, 2025

Pathfinder pass makes unsafe assumption about operator ordering

bugSomething isn't workingSomething isn't working

Status: Open.

#2583 In Xilinx/mlir-aie;

· fifield opened on Sep 16, 2025

Runtime Library with TXN address patching to enable >5 buffer objects

Status: Open.

#2582 In Xilinx/mlir-aie;

· Victor-Jung opened on Sep 16, 2025

· 

IRON Release XXX

Port Reuse and Data Merge from ST to CT

Status: Open.

#2580 In Xilinx/mlir-aie;

· AlanWalker159 opened on Sep 14, 2025

Add option to align buffers with the vector length

enhancementNew feature or requestNew feature or request

Status: Open.

#2579 In Xilinx/mlir-aie;

· quim0 opened on Sep 12, 2025

Getting Ryzen AI Software

questionFurther information is requestedFurther information is requested

Status: Open.

#2577 In Xilinx/mlir-aie;

· hungryDodo opened on Sep 11, 2025

Make <code>IRON_CACHE_DIR</code> an environment variable

qualityImprove code quality: maintainability, cleanup, code reorganization.Improve code quality: maintainability, cleanup, code reorganization.

Status: Open.

#2572 In Xilinx/mlir-aie;

· AndraBisca opened on Sep 10, 2025

Missing and Wrong Data Layout Transformation Checks

Status: Open.

#2566 In Xilinx/mlir-aie;

· andrej opened on Sep 5, 2025