Pathfinder pass makes unsafe assumption about operator ordering

[fifield]

AIEPathfinderPass assumes that aie.packet_source always comes before aie.packet_dest in aie.packet_flow regions but there is absolutely no guarantee of ordering.

mlir-aie/lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp

Lines 289 to 305 in 59a4a00

	TileID srcCoords, destCoords;
	for (Operation &Op : b.getOperations()) {
	if (auto pktSource = dyn_cast<PacketSourceOp>(Op)) {
	srcTile = dyn_cast<TileOp>(pktSource.getTile().getDefiningOp());
	srcPort = pktSource.port();
	srcCoords = {srcTile.colIndex(), srcTile.rowIndex()};
	} else if (auto pktDest = dyn_cast<PacketDestOp>(Op)) {
	destTile = dyn_cast<TileOp>(pktDest.getTile().getDefiningOp());
	destPort = pktDest.port();
	destCoords = {destTile.colIndex(), destTile.rowIndex()};
	// Assign "keep_pkt_header flag"
	auto keep = pktFlowOp.getKeepPktHeader();
	keepPktHeaderAttr[{destTile, destPort}] =
	keep ? BoolAttr::get(Op.getContext(), *keep) : nullptr;
	TileID srcSB = {srcCoords.col, srcCoords.row};

Worse, srcCoords will be used uninitialized when this is not the case (line 305). In practice it crashes:

$ cat pkt.mlir
module {
  %tile_1_3 = aie.tile(1, 3)
  %tile_2_4 = aie.tile(2, 4)
  aie.packet_flow(16) {
    aie.packet_dest<%tile_1_3, DMA : 1>
    aie.packet_dest<%tile_2_4, DMA : 1>
    aie.packet_source<%tile_1_3, DMA : 0>
  } {keep_pkt_header = true}
}
$ aiecc.py pkt.mlir 
aie-opt: /work/mlir-aie/lib/Dialect/AIE/Transforms/AIEPathFinder.cpp:620: virtual std::optional<std::map<xilinx::AIE::PathEndPoint, std::map<xilinx::AIE::TileID, xilinx::AIE::SwitchSetting> > > xilinx::AIE::Pathfinder::findPaths(int): Assertion `i < sb.srcPorts.size()' failed.