RISC-V

Implementation of RISC-V architecture using Verilog. The architecture is of single process without pipelining.

To write the command/ code to the processor

1.Add the up code to the reg mem[] located inside of instructionmemory.v

To run the code

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
ALU.v		ALU.v
ALudecoder.v		ALudecoder.v
Extender.v		Extender.v
I_TYPE.gtkw		I_TYPE.gtkw
Imm_RegMux.v		Imm_RegMux.v
PC_adder.v		PC_adder.v
RD_WD3Mux.v		RD_WD3Mux.v
README.md		README.md
Regfile.v		Regfile.v
Single_Cycle_Tb.v		Single_Cycle_Tb.v
Single_Cycle_Top.v		Single_Cycle_Top.v
contorl_top.v		contorl_top.v
datamem.v		datamem.v
instructionmemory.v		instructionmemory.v
main_decoder1.v		main_decoder1.v
output.out		output.out
programcounter.v		programcounter.v

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