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bebarinobebarino
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Merge branches 'clk-nvidia', 'clk-imx', 'clk-samsung' and 'clk-qcom' into clk-next
* clk-nvidia: clk: tegra: Support runtime PM and power domain clk: tegra: Make vde a child of pll_p on tegra114 * clk-imx: clk: imx8mp: Fix the parent clk of the audio_root_clk clk: imx8mp: Remove IPG_AUDIO_ROOT from imx8mp-clock.h clk: imx8mn: Fix imx8mn_clko1_sels clk: imx: Use div64_ul instead of do_div clk: imx: imx8ulp: set suppress_bind_attrs to true * clk-samsung: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks * clk-qcom: (25 commits) clk: qcom: gcc-sc7280: Mark gcc_cfg_noc_lpass_clk always enabled clk: qcom: clk-alpha-pll: Increase PLL lock detect poll time clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock ...
5 parents 151768f + fcfc6ea + 176a320 + 14350ed + 87e5570 commit f691c9b

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‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on MSM8976.
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See also:
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- dt-bindings/clock/qcom,gcc-msm8976.h
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properties:
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compatible:
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enum:
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- qcom,gcc-msm8976
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- qcom,gcc-msm8976-v1.1
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clocks:
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items:
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- description: XO source
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- description: Always-on XO source
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Byte clock from DSI PHY1
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clock-names:
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items:
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- const: xo
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- const: xo_a
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- const: dsi0pll
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- const: dsi0pllbyte
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- const: dsi1pll
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- const: dsi1pllbyte
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vdd_gfx-supply:
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description:
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Phandle to voltage regulator providing power to the GX domain.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- vdd_gfx-supply
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-msm8976";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x1800000 0x80000>;
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clocks = <&xo_board>,
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<&xo_board>,
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<&dsi0_phy 1>,
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<&dsi0_phy 0>,
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<&dsi1_phy 1>,
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<&dsi1_phy 0>;
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clock-names = "xo",
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"xo_a",
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"dsi0pll",
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"dsi0pllbyte",
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"dsi1pll",
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"dsi1pllbyte";
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vdd_gfx-supply = <&pm8004_s5>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SDX65
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maintainers:
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- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SDX65
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See also:
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- dt-bindings/clock/qcom,gcc-sdx65.h
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properties:
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compatible:
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const: qcom,gcc-sdx65
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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- description: PLL test clock source (Optional clock)
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minItems: 5
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_pipe_clk
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
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- const: core_bi_pll_test_se # Optional clock
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minItems: 5
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x100000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SM8450
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SM8450
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See also:
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- dt-bindings/clock/qcom,gcc-sm8450.h
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properties:
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compatible:
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const: qcom,gcc-sm8450
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source (Optional clock)
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- description: PCIE 1 Pipe clock source (Optional clock)
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- description: PCIE 1 Phy Auxillary clock source (Optional clock)
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- description: UFS Phy Rx symbol 0 clock source (Optional clock)
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
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- description: UFS Phy Tx symbol 0 clock source (Optional clock)
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- description: USB3 Phy wrapper pipe clock source (Optional clock)
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minItems: 2
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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- const: pcie_0_pipe_clk # Optional clock
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- const: pcie_1_pipe_clk # Optional clock
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- const: pcie_1_phy_aux_clk # Optional clock
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- const: ufs_phy_rx_symbol_0_clk # Optional clock
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- const: ufs_phy_rx_symbol_1_clk # Optional clock
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- const: ufs_phy_tx_symbol_0_clk # Optional clock
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
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minItems: 2
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sm8450";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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clock-names = "bi_tcxo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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- qcom,sc8180x-rpmh-clk
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- qcom,sdm845-rpmh-clk
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- qcom,sdx55-rpmh-clk
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- qcom,sdx65-rpmh-clk
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- qcom,sm6350-rpmh-clk
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- qcom,sm8150-rpmh-clk
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- qcom,sm8250-rpmh-clk
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- qcom,sm8350-rpmh-clk
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- qcom,sm8450-rpmh-clk
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clocks:
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maxItems: 1

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