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Merge tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull qcom clk driver updates from Bjorn Andersson: This introduces bindings and drivers for the global clock controllers found in SDX65, SM8450 and MSM8976, as well as RPMh clock support for SDX65 and SM8450. It cleans up the SMD RPM clock driver and it adds includes for clk-provider.h throughout the clock providers that was lacking this. * tag 'qcom-clk-for-5.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (23 commits) clk: qcom: turingcc-qcs404: explicitly include clk-provider.h clk: qcom: q6sstop-qcs404: explicitly include clk-provider.h clk: qcom: mmcc-apq8084: explicitly include clk-provider.h clk: qcom: lpasscc-sdm845: explicitly include clk-provider.h clk: qcom: lpasscc-sc7280: explicitly include clk-provider.h clk: qcom: gcc-sm6350: explicitly include clk-provider.h clk: qcom: gcc-msm8994: explicitly include clk-provider.h clk: qcom: gcc-sm8350: explicitly include clk-provider.h clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver dt-bindings: clk: qcom: Document MSM8976 Global Clock Controller clk: qcom: Add clock driver for SM8450 clk: qcom: Add SDX65 GCC support clk: qcom: Add LUCID_EVO PLL type for SDX65 dt-bindings: clock: Add SM8450 GCC clock bindings dt-bindings: clock: Add SDX65 GCC clock bindings clk: qcom: rpmh: add support for SM8450 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8450 clk: qcom: smd-rpm: Drop binary value handling for buffered clock clk: qcom: smd-rpm: Drop the use of struct rpm_cc clk: qcom: smd-rpm: Drop MFD qcom-rpm reference ...
2 parents 9c33707 + 96ea2a4 commit 87e5570

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‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on MSM8976.
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See also:
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- dt-bindings/clock/qcom,gcc-msm8976.h
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properties:
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compatible:
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enum:
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- qcom,gcc-msm8976
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- qcom,gcc-msm8976-v1.1
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clocks:
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items:
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- description: XO source
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- description: Always-on XO source
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Byte clock from DSI PHY1
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clock-names:
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items:
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- const: xo
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- const: xo_a
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- const: dsi0pll
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- const: dsi0pllbyte
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- const: dsi1pll
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- const: dsi1pllbyte
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vdd_gfx-supply:
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description:
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Phandle to voltage regulator providing power to the GX domain.
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- vdd_gfx-supply
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-msm8976";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x1800000 0x80000>;
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clocks = <&xo_board>,
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<&xo_board>,
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<&dsi0_phy 1>,
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<&dsi0_phy 0>,
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<&dsi1_phy 1>,
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<&dsi1_phy 0>;
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clock-names = "xo",
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"xo_a",
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"dsi0pll",
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"dsi0pllbyte",
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"dsi1pll",
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"dsi1pllbyte";
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vdd_gfx-supply = <&pm8004_s5>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SDX65
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maintainers:
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- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SDX65
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See also:
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- dt-bindings/clock/qcom,gcc-sdx65.h
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properties:
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compatible:
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const: qcom,gcc-sdx65
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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- description: PLL test clock source (Optional clock)
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minItems: 5
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_pipe_clk
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
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- const: core_bi_pll_test_se # Optional clock
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minItems: 5
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x100000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SM8450
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SM8450
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See also:
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- dt-bindings/clock/qcom,gcc-sm8450.h
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properties:
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compatible:
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const: qcom,gcc-sm8450
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source (Optional clock)
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- description: PCIE 1 Pipe clock source (Optional clock)
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- description: PCIE 1 Phy Auxillary clock source (Optional clock)
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- description: UFS Phy Rx symbol 0 clock source (Optional clock)
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- description: UFS Phy Rx symbol 1 clock source (Optional clock)
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- description: UFS Phy Tx symbol 0 clock source (Optional clock)
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- description: USB3 Phy wrapper pipe clock source (Optional clock)
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minItems: 2
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clock-names:
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items:
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- const: bi_tcxo
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- const: sleep_clk
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- const: pcie_0_pipe_clk # Optional clock
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- const: pcie_1_pipe_clk # Optional clock
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- const: pcie_1_phy_aux_clk # Optional clock
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- const: ufs_phy_rx_symbol_0_clk # Optional clock
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- const: ufs_phy_rx_symbol_1_clk # Optional clock
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- const: ufs_phy_tx_symbol_0_clk # Optional clock
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
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minItems: 2
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sm8450";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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clock-names = "bi_tcxo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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- qcom,sc8180x-rpmh-clk
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- qcom,sdm845-rpmh-clk
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- qcom,sdx55-rpmh-clk
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- qcom,sdx65-rpmh-clk
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- qcom,sm6350-rpmh-clk
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- qcom,sm8150-rpmh-clk
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- qcom,sm8250-rpmh-clk
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- qcom,sm8350-rpmh-clk
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- qcom,sm8450-rpmh-clk
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clocks:
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maxItems: 1

‎MAINTAINERS

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@@ -15725,6 +15725,15 @@ F: Documentation/admin-guide/media/qcom_camss.rst
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F: Documentation/devicetree/bindings/media/*camss*
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F: drivers/media/platform/qcom/camss/
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QUALCOMM CLOCK DRIVERS
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M: Bjorn Andersson <bjorn.andersson@linaro.org>
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L: linux-arm-msm@vger.kernel.org
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S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
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F: Documentation/devicetree/bindings/clock/qcom,*
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F: drivers/clk/qcom/
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F: include/dt-bindings/clock/qcom,*
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QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
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M: Niklas Cassel <nks@flawful.org>
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L: linux-pm@vger.kernel.org

‎drivers/clk/qcom/Kconfig

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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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config MSM_GCC_8976
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tristate "MSM8956/76 Global Clock Controller"
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select QCOM_GDSC
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help
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Support for the global clock controller on msm8956/76 devices.
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Say Y if you want to use peripheral devices such as UART, SPI,
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i2c, USB, SD/eMMC, SATA, PCIe, etc.
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config MSM_MMCC_8994
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tristate "MSM8994 Multimedia Clock Controller"
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select MSM_GCC_8994
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Support for the camera clock controller on SM8250 devices.
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Say Y if you want to support camera devices and camera functionality.
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config SDX_GCC_65
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tristate "SDX65 Global Clock Controller"
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select QCOM_GDSC
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help
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Support for the global clock controller on SDX65 devices.
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_DISPCC_8250
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tristate "SM8150 and SM8250 Display Clock Controller"
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depends on SM_GCC_8150 || SM_GCC_8250
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_GCC_8450
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tristate "SM8450 Global Clock Controller"
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select QCOM_GDSC
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help
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Support for the global clock controller on SM8450 devices.
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_GPUCC_8150
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tristate "SM8150 Graphics Clock Controller"
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select SM_GCC_8150

‎drivers/clk/qcom/Makefile

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obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
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obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
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obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
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obj-$(CONFIG_MSM_GCC_8976) += gcc-msm8976.o
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obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
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obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
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obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
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obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
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obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
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obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
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obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
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obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
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obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
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obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
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obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
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obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
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obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
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obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
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obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
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obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o

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