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Merge tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki: - removal of all remaining uses of __clk_lookup() in drivers/clk/samsung - refactoring of the CPU clocks registration to use common interface - an update of the Exynos850 driver (support for more clock domains) required by the E850-96 development board - initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8) * tag 'clk-v5.17-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Add initial Exynos7885 clock driver clk: samsung: clk-pll: Add support for pll1417x clk: samsung: Make exynos850_register_cmu shared dt-bindings: clock: Document Exynos7885 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos7885 CMU clk: samsung: exynos850: Add missing sysreg clocks dt-bindings: clock: Add bindings for Exynos850 sysreg clocks clk: samsung: exynos850: Register clocks early clk: samsung: exynos850: Keep some crucial clocks running clk: samsung: exynos850: Implement CMU_CMGP domain dt-bindings: clock: Add bindings for Exynos850 CMU_CMGP clk: samsung: exynos850: Implement CMU_APM domain dt-bindings: clock: Add bindings for Exynos850 CMU_APM clk: samsung: Update CPU clk registration clk: samsung: Remove meaningless __init and extern from header files clk: samsung: remove __clk_lookup() usage dt-bindings: clock: samsung: add IDs for some core clocks
2 parents fa55b7d + 45bd816 commit 14350ed

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+1503
-185
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‎Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7885 SoC clock controller
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maintainers:
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- Dávid Virág <virag.david003@gmail.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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- Tomasz Figa <tomasz.figa@gmail.com>
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description: |
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Exynos7885 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that root tree
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is an external clock: OSCCLK (26 MHz). This external clock must be defined
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as a fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'dt-bindings/clock/exynos7885.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynos7885-cmu-top
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- samsung,exynos7885-cmu-core
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- samsung,exynos7885-cmu-peri
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clocks:
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minItems: 1
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maxItems: 10
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clock-names:
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minItems: 1
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maxItems: 10
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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clock-names:
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-core
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_CORE bus clock (from CMU_TOP)
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- description: CCI clock (from CMU_TOP)
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- description: G3D clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_core_bus
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- const: dout_core_cci
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- const: dout_core_g3d
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos7885-cmu-peri
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERI bus clock (from CMU_TOP)
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- description: SPI0 clock (from CMU_TOP)
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- description: SPI1 clock (from CMU_TOP)
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- description: UART0 clock (from CMU_TOP)
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- description: UART1 clock (from CMU_TOP)
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- description: UART2 clock (from CMU_TOP)
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- description: USI0 clock (from CMU_TOP)
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- description: USI1 clock (from CMU_TOP)
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- description: USI2 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_peri_bus
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- const: dout_peri_spi0
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- const: dout_peri_spi1
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- const: dout_peri_uart0
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- const: dout_peri_uart1
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- const: dout_peri_uart2
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- const: dout_peri_usi0
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- const: dout_peri_usi1
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- const: dout_peri_usi2
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required:
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- compatible
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- "#clock-cells"
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- clocks
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- clock-names
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- reg
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additionalProperties: false
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examples:
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# Clock controller node for CMU_PERI
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- |
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#include <dt-bindings/clock/exynos7885.h>
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cmu_peri: clock-controller@10010000 {
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compatible = "samsung,exynos7885-cmu-peri";
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reg = <0x10010000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_PERI_BUS>,
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<&cmu_top CLK_DOUT_PERI_SPI0>,
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<&cmu_top CLK_DOUT_PERI_SPI1>,
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<&cmu_top CLK_DOUT_PERI_UART0>,
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<&cmu_top CLK_DOUT_PERI_UART1>,
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<&cmu_top CLK_DOUT_PERI_UART2>,
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<&cmu_top CLK_DOUT_PERI_USI0>,
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<&cmu_top CLK_DOUT_PERI_USI1>,
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<&cmu_top CLK_DOUT_PERI_USI2>;
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clock-names = "oscclk",
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"dout_peri_bus",
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"dout_peri_spi0",
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"dout_peri_spi1",
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"dout_peri_uart0",
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"dout_peri_uart1",
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"dout_peri_uart2",
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"dout_peri_usi0",
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"dout_peri_usi1",
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"dout_peri_usi2";
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};
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...

‎Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

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compatible:
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enum:
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- samsung,exynos850-cmu-top
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- samsung,exynos850-cmu-apm
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- samsung,exynos850-cmu-cmgp
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- samsung,exynos850-cmu-core
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- samsung,exynos850-cmu-dpu
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- samsung,exynos850-cmu-hsi
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items:
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- const: oscclk
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-apm
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_APM bus clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: dout_clkcmu_apm_bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos850-cmu-cmgp
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_CMGP bus clock (from CMU_APM)
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clock-names:
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items:
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- const: oscclk
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- const: gout_clkcmu_cmgp_bus
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- if:
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properties:
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compatible:

‎drivers/clk/samsung/Makefile

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@@ -16,7 +16,9 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
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obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
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obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o

‎drivers/clk/samsung/clk-cpu.c

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}
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/* helper function to register a CPU clock */
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name,
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
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unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,

‎drivers/clk/samsung/clk-cpu.h

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#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
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};
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name,
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
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unsigned long offset,
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const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags);
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#endif /* __SAMSUNG_CLK_CPU_H */

‎drivers/clk/samsung/clk-exynos-arm64.c

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021 Linaro Ltd.
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* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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* Author: Dávid Virág <virag.david003@gmail.com>
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*
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* This file contains shared functions used by some arm64 Exynos SoCs,
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* such as Exynos7885 or Exynos850 to register and init CMUs.
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*/
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#include <linux/clk.h>
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#include <linux/of_address.h>
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#include "clk-exynos-arm64.h"
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/* Gate register bits */
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#define GATE_MANUAL BIT(20)
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#define GATE_ENABLE_HWACG BIT(28)
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/* Gate register offsets range */
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#define GATE_OFF_START 0x2000
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#define GATE_OFF_END 0x2fff
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/**
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* exynos_arm64_init_clocks - Set clocks initial configuration
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* @np: CMU device tree node with "reg" property (CMU addr)
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* @reg_offs: Register offsets array for clocks to init
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* @reg_offs_len: Number of register offsets in reg_offs array
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*
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* Set manual control mode for all gate clocks.
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*/
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static void __init exynos_arm64_init_clocks(struct device_node *np,
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const unsigned long *reg_offs, size_t reg_offs_len)
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{
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void __iomem *reg_base;
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size_t i;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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for (i = 0; i < reg_offs_len; ++i) {
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void __iomem *reg = reg_base + reg_offs[i];
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u32 val;
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/* Modify only gate clock registers */
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if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
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continue;
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val = readl(reg);
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val |= GATE_MANUAL;
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val &= ~GATE_ENABLE_HWACG;
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writel(val, reg);
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}
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iounmap(reg_base);
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}
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/**
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* exynos_arm64_register_cmu - Register specified Exynos CMU domain
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* @dev: Device object; may be NULL if this function is not being
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* called from platform driver probe function
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* @np: CMU device tree node
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* @cmu: CMU data
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*
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* Register specified CMU domain, which includes next steps:
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*
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* 1. Enable parent clock of @cmu CMU
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* 2. Set initial registers configuration for @cmu CMU clocks
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* 3. Register @cmu CMU clocks using Samsung clock framework API
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*/
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void __init exynos_arm64_register_cmu(struct device *dev,
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struct device_node *np, const struct samsung_cmu_info *cmu)
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{
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/* Keep CMU parent clock running (needed for CMU registers access) */
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if (cmu->clk_name) {
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struct clk *parent_clk;
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if (dev)
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parent_clk = clk_get(dev, cmu->clk_name);
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else
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parent_clk = of_clk_get_by_name(np, cmu->clk_name);
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if (IS_ERR(parent_clk)) {
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pr_err("%s: could not find bus clock %s; err = %ld\n",
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__func__, cmu->clk_name, PTR_ERR(parent_clk));
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} else {
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clk_prepare_enable(parent_clk);
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}
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}
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exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
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samsung_cmu_register_one(np, cmu);
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}

‎drivers/clk/samsung/clk-exynos-arm64.h

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Linaro Ltd.
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* Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
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* Author: Sam Protsenko <semen.protsenko@linaro.org>
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* Author: Dávid Virág <virag.david003@gmail.com>
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*
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* This file contains shared functions used by some arm64 Exynos SoCs,
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* such as Exynos7885 or Exynos850 to register and init CMUs.
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*/
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#ifndef __CLK_EXYNOS_ARM64_H
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#define __CLK_EXYNOS_ARM64_H
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#include "clk.h"
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void exynos_arm64_register_cmu(struct device *dev,
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struct device_node *np, const struct samsung_cmu_info *cmu);
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#endif /* __CLK_EXYNOS_ARM64_H */

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