32-bit Single-Cycle MIPS Processor in Verilog using Xilinx ISE

This project is a 32-bit single-cycle MIPS processor simulated using Xilinx ISE Design Suite 14.5. It was developed as part of my semester project at NUST College of EME for the Computer Organization and Architecture course.

The processor is capable of performing integer operations, but does not include a Floating Point Unit (FPU).

You can download the MIPS folder, open it as a project in Xilinx ISE, and simulate the processor.

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🧠 Key Features

• 32-bit Single-Cycle Architecture
• Performs basic integer operations (addition, subtraction, etc.)
• Does not include a Floating Point Unit (FPU)
• Simulated on Xilinx ISE Design Suite 14.5
• Written in Verilog HDL

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📊 Schematic

Below is the schematic of the processor that this project is based on:

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🖼️ Simulation Screenshots

Here are some simulation results from Xilinx ISE:

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🚀 How to Run

1. Download the MIPS folder from this repository.
2. Open the folder in Xilinx ISE Design Suite 14.5.
3. Simulate the processor and verify its functionality using the provided testbenches.

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📜 License

This project is licensed under the MIT License. See LICENSE.md for more details.

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🤝 Contributions

If you want to collaborate, provide feedback, or make improvements to this project, feel free to open an issue or create a pull request.