Asynchronous FIFO Design

Overview

This repository contains a VHDL implementation of an Asynchronous FIFO, designed to facilitate data transfer between two systems operating on different clock frequencies. The design uses gray code pointers to ensure safe synchronization across clock domains, making it ideal for clock domain crossing applications.

Features

• Configurable data width and FIFO depth.
• Uses gray code pointers for reliable cross-domain synchronization.
• Includes a testbench to verify write/read operations and full/empty conditions.

Files

• async_fifo.vhd: VHDL code for the Asynchronous FIFO.
• tb_async_fifo.vhd: Testbench to simulate and verify the FIFO behavior.

Usage

1. Compile the async_fifo.vhd and tb_async_fifo.vhd files using a VHDL simulator (e.g., ModelSim, GHDL).
2. Run the simulation to observe the FIFO's behavior with different clock frequencies.
3. Adjust the DATA_WIDTH and FIFO_DEPTH generics in async_fifo.vhd as needed.