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1. FIFO FIFO Public

   Asynchronous FIFO implementation in VHDL, designed to synchronize data transfer between two different clock domains using gray code pointers. Includes a comprehensive testbench to verify functional…

   VHDL 1

2. UART UART Public

   A modular Verilog UART implementation for serial communication, featuring a transmitter, receiver, baud rate generator, and testbench, designed for 8-bit data at 9600 baud with a 50 MHz clock.

   Verilog

3. MIPS MIPS Public

   The project focuses on understanding and building the VeriRISC architecture, featuring a three-bit opcode and five-bit operand, supporting eight instructions and a 32-location address space. The de…

   Verilog