Digital Design Projects in Verilog

This repository contains a collection of digital design projects developed in Verilog HDL. These projects were initially written, tested, and simulated on EDA Playground, a web-based IDE for hardware design and verification.

🔧 Tools Used

• Language: Verilog HDL (IEEE Std 1364-2001)
• Simulator: EDA Playground (e.g., Icarus Verilog, Synopsys VCS, etc.)
• Waveform Viewer: GTKWave (where applicable)

📁 Project Structure

Each folder contains the following:

• Verilog source files (.v)
• Testbenches for functional verification
• Simulation files, etc.

📋 List of Digital Designs

Below are the Verilog modules currently available in this repository:

• All logic gates including NOT, AND, OR, NAND, NOR, XOR, XNOR
• Combinational Circuits including Half Adder, Full Adder, Multiplexers, Encoder, Decoder, Binary to Gray Conv, Gray to Binary Conv, Bidirectional Buffer, etc.
• Sequential Circuits including Flip Flops (SR, JK, D, T), Synchronizer, etc
• Modelling Styles, .
• 16x8 Dual Port RAM (Single Clock+Testcases, Two Clock, and with Self-Checking Testbench), etc.
• 8x8 Synchronous FIFO Design (With testcases and self-checking testbench), etc.
• 110100 Sequence Detector FSM Design, etc.
• More coming soon...

✨ Feel free to contribute by improving the designs, adding testbenches, or suggesting new modules.

How to Run this Projects?

• Just open EDA playground, write or copy-paste these verilog+testbench codes on EDA, and simulate it.

Contact me

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