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1. Synchronous-FIFO-Design-in-Verilog Synchronous-FIFO-Design-in-Verilog Public

   This project implements an **8-depth, 8-bit wide Synchronous FIFO (First-In First-Out)** memory buffer in **Verilog HDL**. FIFO is a fundamental memory structure used widely in digital systems to h…

   SystemVerilog

2. Dual-Port-RAM Dual-Port-RAM Public

   This repository contains three versions of a **16x8 Dual-Port RAM** designed in Verilog HDL, progressing from basic to advanced concepts. Each version builds on the previous one, introducing new te…

   SystemVerilog

3. APB-Master-Slave-Verilog-Simulation-Project APB-Master-Slave-Verilog-Simulation-Project Public

   Welcome to the APB (Advanced Peripheral Bus) Master-Slave implementation in Verilog RTL! 🎯 This project demonstrates the full APB protocol including master and slave FSM-based logic with memory ope…

   SystemVerilog

4. Carry-Skip-Adder-FPGA-Project Carry-Skip-Adder-FPGA-Project Public

   This repository contains the Verilog HDL implementation of a 2-bit Carry Skip Adder (CSKA) and its deployment on an FPGA using Xilinx Vivado. This project demonstrates how to design, simulate, synt…

   SystemVerilog

5. Digital-Design-Projects-in-Verilog Digital-Design-Projects-in-Verilog Public

   This repository contains a collection of digital design projects developed in Verilog HDL. These projects were initially written, tested, and simulated on EDA Playground, a web-based IDE for hardwa…

   SystemVerilog

6. rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys rtl-design-and-synthesis-using-icarus-verilog-gtkwave-yosys Public

   A collection of Verilog-based RTL design projects with testbenches, simulated using Icarus Verilog and GTKWave. This repo showcases foundational digital logic circuits as part of my VLSI learning j…

   Verilog