This project is centered around a synchronous counter which functions as a resetting clock. It consists of three individual counters for seconds, minutes, and hours, with each counter triggered when the previous one is filled. The clock module produces a periodic signal of 1Hz frequency by dividing the built-in clock frequency of 50MHz. The alarm inputs are set with a precision of 1 minute, and a buzzer is incorporated to sound the alarm. The circuits are developed and modeled using Verilog Hardware Description Language, and the implementation is accomplished on an FPGA kit provided by Intel Corporation called DE-10 Lite.
The core of this project is a resetting clock that employs a synchronous counter. It comprises three separate counters for seconds, minutes, and hours, each triggered upon reaching its maximum value. A clock module generates a 1Hz frequency signal by dividing the built-in 50MHz clock frequency. An alarm is incorporated that operates with 1-minute precision and features a buzzer to notify the user. The circuits are created and simulated using Verilog Hardware Description Language, and the project is implemented on an FPGA board provided by Intel Corporation known as DE-10 Lite.