🎯 About Me
- 🧑🎓 ECE undergrad from Dayananda Sagar College of Engineering, Bengaluru
- 🔧 Trained in ASIC/FPGA RTL Design & Verification using Verilog, SystemVerilog & UVM
- 🛠️ Experienced with industry-standard EDA tools: Cadence Xcelium, Synopsys VCS, Xilinx Vivado, Quartus Prime, ModelSim, Genus
- 🌐 Passionate about Digital VLSI, RTL Design, Functional Verification, FPGA Prototyping, and SoC Development
🛠️ Core Skills
HDL & HVL
Verification & Methodologies
EDA Tools
Protocols
Core Concepts
Prgramming Languages
🏢 Internships
-
TriSpace Technologies (Feb–May 2025)
- Designed & verified a FPU (single & double precision)
- RTL was simulated using Cadence Xcelium tool
-
Excel VLSI Technologies (Nov 2023)
- Learnt about IP design and Verification done in the industry including
- Designed basic blocks such as ALU, Clock Divider, APB Memory, Asynchrnous FIFO
💻 Training
- Maven Silicon
- Trained and learnt on Digital Design, Verilog HDL, SystemVerilog, UVM, Assertion-based Verification
🏆 Achievements
- 🥇 1st Place – RTL Design & Verification Contest (IEEE DSCE)
- 🏆 1st Prize – PPM Project in Communication Systems Exhibition
- 👨💼 Lead the Digital VLSI Team, The Point Seven Club, DSCE
📜 Certifications
- Digital Design using Verilog – IIT Guwahati
- Digital Electronic Circuits – IIT Kharagpur
- FPGA Design – University of Colorado Boulder
- VLSI for Beginners – NIELIT Calicut
📫 Let's Connect
- 📬 Email: abhinavsundriyal08@gmail.com
- 📂 Resume (Google Drive)
📈 GitHub Stats
🚀 "Driven by logic. Powered by silicon."