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Add Basic support for Microchip SAM D5X/E5X Family devices #93450
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west.yml: Update west.yml for SAM_D5X_E5X dfp
ArunMCHP 1b5a379
dts: arm: microchip: add dtsi files for Microchip SAM D5x/E5x SoC series
ArunMCHP ba85f35
soc: microchip: add support for SAM D5x/E5x SoC series
ArunMCHP b6ce2b5
dts: arm: microchip: add clock dts node and bindings for SAM D5x/E5x
sunil-abraham 8c14d59
drivers: clock_control: microchip: clock support for SAM D5x/E5x
sunil-abraham 7158b69
dts: arm: microchip: add pinctrl dts node and bindings for Port G1 IP
AzharMCHP 4261412
drivers: pinctrl: microchip: add pinctrl driver for Port G1 IP
AzharMCHP f292fe1
dts: arm: microchip: add uart dts node and bindings for sercom g1 IPs
sunil-abraham b34b28a
drivers: uart: microchip: add minimal support for sercom uart g1 IPs
sunil-abraham 9afa45c
boards: microchip: add SAM E54 Xplained Pro board support
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config BOARD_SAM_E54_XPRO | ||
select SOC_ATSAME54P20A |
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) |
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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board: | ||
name: sam_e54_xpro | ||
full_name: SAM E54 Xplained Pro | ||
vendor: microchip | ||
socs: | ||
- name: atsame54p20a |
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.. zephyr:board:: sam_e54_xpro | ||
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SAM E54 Xplained Pro Evaluation Kit | ||
################################### | ||
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Overview | ||
******** | ||
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The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and | ||
prototyping with the SAM E54 Cortex®-M4F processor-based | ||
microcontrollers. The kit includes Microchip’s Embedded Debugger (EDBG), | ||
which provides a full debug interface without the need for additional | ||
hardware. | ||
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.. image:: img/atsam_e54_xpro.webp | ||
:align: center | ||
:alt: SAM_E54_XPRO | ||
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Hardware | ||
******** | ||
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- ATSAME54P20A ARM Cortex-M4F processor at 120 MHz | ||
- 32.768 kHz crystal oscillator | ||
- 12 MHz crystal oscillator | ||
- 1024 KiB flash memory and 256 KiB of RAM | ||
- One yellow user LED | ||
- One mechanical user push button | ||
- One reset button | ||
- On-board USB based EDBG unit with serial console | ||
- One QTouch® PTC button | ||
- 32 MiB QSPI Flash | ||
- ATECC508 CryptoAuthentication™ device | ||
- AT24MAC402 serial EEPROM with EUI-48™ MAC address | ||
- Ethernet | ||
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- RJ45 connector with built-in magnetics | ||
- KSZ8091RNA PHY | ||
- 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver | ||
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- USB interface, host, and device | ||
- SD/SDIO card connector | ||
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Supported Features | ||
================== | ||
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.. zephyr:board-supported-hw:: | ||
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The default configuration can be found in the Kconfig | ||
:zephyr_file:`boards/microchip/sam/sam_e54_xpro/sam_e54_xpro_defconfig`. | ||
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Pin Mapping | ||
=========== | ||
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The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These | ||
controllers are responsible for pin muxing, input/output, pull-up, etc. | ||
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For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 | ||
Xplained Pro Schematic`_. | ||
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.. image:: img/atsam_e54_xpro_pinout.webp | ||
:align: center | ||
:alt: SAME54-XPRO-pinout | ||
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Default Zephyr Peripheral Mapping: | ||
---------------------------------- | ||
- SERCOM2 USART TX : PB24 | ||
- SERCOM2 USART RX : PB25 | ||
- GPIO/PWM LED0 : PC18 | ||
- GPIO SW0 : PB31 | ||
- GMAC RMII REFCK : PA14 | ||
- GMAC RMII TXEN : PA17 | ||
- GMAC RMII TXD0 : PA18 | ||
- GMAC RMII TXD1 : PA19 | ||
- GMAC RMII CRSDV : PC20 | ||
- GMAC RMII RXD0 : PA13 | ||
- GMAC RMII RXD1 : PA12 | ||
- GMAC RMII RXER : PA15 | ||
- GMAC MDIO MDC : PC11 | ||
- GMAC MDIO MDIO : PC12 | ||
- SERCOM4 SPI SCK : PB26 | ||
- SERCOM4 SPI MOSI : PB27 | ||
- SERCOM4 SPI MISO : PB29 | ||
- SERCOM7 I2C SDA : PD08 | ||
- SERCOM7 I2C SCL : PD09 | ||
- USB DP : PA25 | ||
- USB DM : PA24 | ||
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System Clock | ||
============ | ||
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The SAME54 MCU is configured to use the 32.768 kHz external oscillator | ||
with the on-chip PLL generating the 48 MHz system clock. | ||
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Serial Port | ||
=========== | ||
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The SAME54 MCU has 8 SERCOM based USARTs with one configured as USARTs in | ||
this BSP. SERCOM2 is the default Zephyr console. | ||
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- SERCOM2 115200 8n1 connected to the onboard Microchip Embedded Debugger (EDBG) | ||
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Programming and Debugging | ||
************************* | ||
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The SAM E54 Xplained Pro comes with a Microchip Embedded Debugger (EDBG). This | ||
provides a debug interface to the SAME54 chip and is supported by | ||
OpenOCD. | ||
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Flashing | ||
======== | ||
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#. Build the Zephyr kernel and the ``hello_world`` sample application: | ||
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.. zephyr-app-commands:: | ||
:zephyr-app: samples/hello_world | ||
:board: sam_e54_xpro | ||
:goals: build | ||
:compact: | ||
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#. Connect the SAM E54 Xplained Pro to your host computer using the USB debug | ||
port. | ||
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#. Run your favorite terminal program to listen for output. Under Linux the | ||
terminal should be :code:`/dev/ttyACM0`. For example: | ||
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.. code-block:: console | ||
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$ minicom -D /dev/ttyACM0 -o | ||
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The -o option tells minicom not to send the modem initialization | ||
string. Connection should be configured as follows: | ||
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- Speed: 115200 | ||
- Data: 8 bits | ||
- Parity: None | ||
- Stop bits: 1 | ||
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#. To flash an image: | ||
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.. zephyr-app-commands:: | ||
:zephyr-app: samples/hello_world | ||
:board: sam_e54_xpro | ||
:goals: flash | ||
:compact: | ||
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You should see "Hello World! same_54_xpro" in your terminal. | ||
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References | ||
********** | ||
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.. target-notes:: | ||
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.. _Microchip website: | ||
http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO | ||
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.. _SAM D5x/E5x Family Datasheet: | ||
http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf | ||
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.. _SAM E54 Xplained Pro Schematic: | ||
http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip |
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boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi
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/* | ||
* Copyright (c) 2025 Microchip Technology Inc. | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <dt-bindings/sam/sam_d5x_e5x/same54/atsame54p20a-pinctrl.h> | ||
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&pinctrl { | ||
sercom2_uart_default: sercom2_uart_default { | ||
group1 { | ||
pinmux = <PB25D_SERCOM2_PAD0>, | ||
<PB24D_SERCOM2_PAD1>; | ||
}; | ||
}; | ||
}; |
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/* | ||
* Copyright (c) 2025 Microchip Technology Inc. | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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/dts-v1/; | ||
#include <microchip/sam/sam_d5x_e5x/same54/atsame54p20a.dtsi> | ||
#include "sam_e54_xpro-pinctrl.dtsi" | ||
#include <zephyr/dt-bindings/input/input-event-codes.h> | ||
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/ { | ||
model = "SAM E54 Xplained Pro"; | ||
compatible = "same54,xpro", "microchip,atsame54p20a", "microchip,same54"; | ||
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chosen { | ||
zephyr,console = &sercom2; | ||
zephyr,shell-uart = &sercom2; | ||
zephyr,sram = &sram0; | ||
zephyr,flash = &flash0; | ||
}; | ||
}; | ||
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&flash0 { | ||
partitions { | ||
compatible = "fixed-partitions"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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/* | ||
* The final 16 KiB is reserved for the application. | ||
* Storage partition will be used by FCB/LittleFS/NVS | ||
* if enabled. | ||
*/ | ||
storage_partition: partition@fc000 { | ||
label = "storage"; | ||
reg = <0x000fc000 0x00004000>; | ||
}; | ||
}; | ||
}; | ||
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&cpu0 { | ||
clock-frequency = <48000000>; | ||
}; | ||
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&sercom2 { | ||
status = "okay"; | ||
compatible = "microchip,sercom-g1-uart"; | ||
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current-speed = <115200>; | ||
data-bits = <8>; | ||
parity = "none"; | ||
stop-bits = "1"; | ||
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rxpo = <1>; | ||
txpo = <0>; | ||
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#address-cells = <1>; | ||
#size-cells = <0>; | ||
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pinctrl-0 = <&sercom2_uart_default>; | ||
pinctrl-names = "default"; | ||
}; |
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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identifier: sam_e54_xpro | ||
name: SAM E54 Xplained Pro | ||
type: mcu | ||
arch: arm | ||
toolchain: | ||
- zephyr | ||
- gnuarmemb | ||
- xtools | ||
flash: 1024 | ||
ram: 256 | ||
supported: | ||
- pinctrl | ||
- shell | ||
- uart | ||
vendor: microchip |
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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CONFIG_BUILD_OUTPUT_HEX=y | ||
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CONFIG_ARM_MPU=y | ||
CONFIG_HW_STACK_PROTECTION=y | ||
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CONFIG_CONSOLE=y | ||
CONFIG_SERIAL=y | ||
CONFIG_UART_CONSOLE=y |
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# Copyright (c) 2025 Microchip Technology Inc. | ||
# SPDX-License-Identifier: Apache-2.0 | ||
source [find interface/cmsis-dap.cfg] | ||
transport select swd | ||
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# chip name | ||
set CHIPNAME same54p20a | ||
set ENDIAN little | ||
set CPUTAPID 0x0bc11477 | ||
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source [find target/atsame5x.cfg] | ||
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reset_config none | ||
cortex_m reset_config sysresetreq | ||
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$_TARGETNAME configure -event gdb-attach { | ||
echo "Debugger attaching: halting execution" | ||
reset halt | ||
gdb_breakpoint_override hard | ||
} | ||
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$_TARGETNAME configure -event gdb-detach { | ||
echo "Debugger detaching: resuming execution" | ||
resume | ||
} |
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# Copyright (c) 2025 Microchip Technology Inc. | ||||
# SPDX-License-Identifier: Apache-2.0 | ||||
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# Symbol for enabling clock driver for a family | ||||
config CLOCK_CONTROL_MCHP_SAM_D5X_E5X | ||||
bool | ||||
default y | ||||
depends on DT_HAS_MICROCHIP_SAM_D5X_E5X_CLOCK_ENABLED | ||||
help | ||||
This symbol define clock driver for Microchip SAM_D5X_E5X family. | ||||
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# Define menu symbol for configuring clock features | ||||
menuconfig CLOCK_CONTROL_MCHP | ||||
bool "Microchip clock controller driver" | ||||
default y | ||||
depends on CLOCK_CONTROL_MCHP_SAM_D5X_E5X | ||||
help | ||||
Enable support for Microchip clock controller driver. | ||||
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# Common features for all SOC families | ||||
if CLOCK_CONTROL_MCHP | ||||
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# Enable get rate API. Since, clock rate for multiple levels of clock sources are to be | ||||
# calculated, this feature consumes some program size, and can be optional. | ||||
config CLOCK_CONTROL_MCHP_GET_RATE | ||||
bool "Get clock rate" | ||||
default y | ||||
help | ||||
This option enables get rate API. | ||||
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endif # CLOCK_CONTROL_MCHP |
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why is this special ?
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Since the clock rates for multiple levels of clock sources need to be calculated, this feature increases the program size. Therefore, it has been made optional, allowing the user to decide whether to enable it.