imx943 netc support on A55

boards/nxp/imx943_evk/Kconfig.defconfig

@@ -1,12 +1,80 @@
 # Copyright 2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+if SOC_MIMX94398_A55
+
+if ETH_NXP_IMX_NETC
+
+config GIC_V3_ITS
+	default y
+
+endif # ETH_NXP_IMX_NETC
+
+# GIC ITS depends on kernel heap which init priority is 30, so set
+# GIC to be 31, mailbox and SCMI will be initialized by the order
+# according to dts dependency although they use the same init priority.
+config INTC_INIT_PRIORITY
+	default 31
+
+config MBOX_INIT_PRIORITY
+	default 31
+
+config ARM_SCMI_SHMEM_INIT_PRIORITY
+	default 31 if SOC_MIMX94398_A55
+
+config ARM_SCMI_TRANSPORT_INIT_PRIORITY
+	default 31 if SOC_MIMX94398_A55
+
+config CLOCK_CONTROL_INIT_PRIORITY
+	default 31 if SOC_MIMX94398_A55
+
+# Enlarge default networking stack
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config NET_TX_STACK_SIZE
+	default 8192
+
+config NET_RX_STACK_SIZE
+	default 8192
+
+if NET_TCP
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 8192
+
+endif # NET_TCP
+
+if NET_MGMT_EVENT
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 8192
+
+endif # NET_MGMT_EVENT
+
+if NET_SOCKETS_SERVICE
+
+config NET_SOCKETS_SERVICE_STACK_SIZE
+	default 8192
+
+endif # NET_SOCKETS_SERVICE
+
+endif # NETWORKING
+
+endif # SOC_MIMX94398_A55
+
+if SOC_MIMX94398_M33
+
 config INTC_INIT_PRIORITY
 	default 2
 
 config MBOX_INIT_PRIORITY
 	default 3
 
+endif # SOC_MIMX94398_M33
+
 if ETH_NXP_IMX_NETC
 
 config ETH_NXP_IMX_RX_RING_LEN

boards/nxp/imx943_evk/board.c

@@ -10,7 +10,7 @@
 
 static int board_init(void)
 {
-#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
+#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) & !defined(CONFIG_CPU_CORTEX_A)
 	/*
 	 * PCS(Physical Coding Sublayer) protocols on link0-5,
 	 * xxxx xxxx xxxx xxx1: 1G SGMII

boards/nxp/imx943_evk/imx943_evk_mimx94398_a55.dts

@@ -35,7 +35,7 @@
 	};
 
 	dram: memory@d0000000 {
-		reg = <0xd0000000 DT_SIZE_M(1)>;
+		reg = <0xd0000000 DT_SIZE_M(10)>;
 	};
 };
 
@@ -45,3 +45,67 @@
 	pinctrl-0 = <&lpuart1_default>;
 	pinctrl-names = "default";
 };
+
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	phy0: phy@f {
+		compatible = "ethernet-phy";
+		reg = <0xf>;
+		status = "disabled";
+	};
+
+	phy1: phy@10 {
+		compatible = "ethernet-phy";
+		reg = <0x10>;
+		status = "disabled";
+	};
+
+	phy2: phy@5 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x5>;
+		status = "okay";
+	};
+
+	phy3: phy@6 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x6>;
+		status = "okay";
+	};
+
+	phy4: phy@7 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x7>;
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	pinctrl-0 = <&eth2_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy2>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enetc_psi1 {
+	pinctrl-0 = <&eth3_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy3>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enetc_psi2 {
+	pinctrl-0 = <&eth4_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy4>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&netc_ptp_clock0 {
+	status = "okay";
+};

boards/nxp/imx95_evk/Kconfig.defconfig

@@ -0,0 +1,66 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX9596_A55
+
+if ETH_NXP_IMX_NETC
+
+config GIC_V3_ITS
+	default y
+
+endif # ETH_NXP_IMX_NETC
+
+# GIC ITS depends on kernel heap which init priority is 30, so set
+# GIC to be 31, mailbox and SCMI will be initialized by the order
+# according to dts dependency although they use the same init priority.
+config INTC_INIT_PRIORITY
+	default 31
+
+config MBOX_INIT_PRIORITY
+	default 31
+
+config ARM_SCMI_SHMEM_INIT_PRIORITY
+	default 31
+
+config ARM_SCMI_TRANSPORT_INIT_PRIORITY
+	default 31
+
+config CLOCK_CONTROL_INIT_PRIORITY
+	default 31
+
+# Enlarge default networking stack
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config NET_TX_STACK_SIZE
+	default 8192
+
+config NET_RX_STACK_SIZE
+	default 8192
+
+if NET_TCP
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 8192
+
+endif # NET_TCP
+
+if NET_MGMT_EVENT
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 8192
+
+endif # NET_MGMT_EVENT
+
+if NET_SOCKETS_SERVICE
+
+config NET_SOCKETS_SERVICE_STACK_SIZE
+	default 8192
+
+endif # NET_SOCKETS_SERVICE
+
+endif # NETWORKING
+
+endif # SOC_MIMX9596_A55

boards/nxp/imx95_evk/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -10,21 +10,6 @@
 
 static int board_init(void)
 {
-#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
-	/* Port 0 to 2 protocol configure: RGMII, RGMII, XGMII */
-	BLK_CTRL_NETCMIX->CFG_LINK_MII_PROT = 0x00000522;
-	BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 = 0x00000040;
-
-	/* Unlock the IERB. It will warm reset whole NETC. */
-	NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
-	while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) {
-	}
-
-	/* Lock the IERB. */
-	NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK;
-	while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) {
-	}
-#endif
 	return 0;
 }
 

boards/nxp/imx95_evk/doc/index.rst

@@ -106,9 +106,10 @@ Ethernet
 --------
 
 NETC driver supports to manage the Physical Station Interface (PSI).
-The first ENET1 port could be enabled for M7 by west build option
-``-DEXTRA_DTC_OVERLAY_FILE=enetc_psi0.overlay``.
+The first ENET1 port could be enabled on M7 DDR and A55 platforms.
 
+For A55 Core, NETC depends on GIC ITS, so need to make sure to allocate heap memory to
+be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE.
 
 Programming and Debugging (A55)
 *******************************

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts

@@ -43,10 +43,35 @@
 	};
 
 	dram: memory@d0000000 {
-		reg = <0xd0000000 DT_SIZE_M(1)>;
+		reg = <0xd0000000 DT_SIZE_M(10)>;
 	};
 };
 
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	phy0: phy@1 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x1>;
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enetc_ptp_clock {
+	status = "okay";
+};
+
 &lpi2c5 {
 	pinctrl-0 = <&lpi2c5_default>;
 	pinctrl-names = "default";

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig

@@ -31,5 +31,3 @@ CONFIG_CLOCK_CONTROL=y
 
 CONFIG_MBOX=y
 CONFIG_ARM_SCMI=y
-CONFIG_INTC_INIT_PRIORITY=2
-CONFIG_MBOX_INIT_PRIORITY=3

boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,12 +26,12 @@
 &emdio {
 	pinctrl-0 = <&emdio_default>;
 	pinctrl-names = "default";
-	status = "disabled";
+	status = "okay";
 
 	phy0: phy@1 {
 		compatible = "realtek,rtl8211f";
 		reg = <0x1>;
-		status = "disabled";
+		status = "okay";
 	};
 };
 
@@ -41,7 +41,11 @@
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
 	phy-connection-type = "rgmii";
-	status = "disabled";
+	status = "okay";
+};
+
+&enetc_ptp_clock {
+	status = "okay";
 };
 
 &flexspi {

drivers/ethernet/nxp_imx_netc/CMakeLists.txt

@@ -4,6 +4,7 @@
 if(CONFIG_ETH_NXP_IMX_NETC)
   zephyr_library_sources(eth_nxp_imx_netc.c)
   zephyr_library_sources(eth_nxp_imx_netc_psi.c)
+  zephyr_library_sources_ifdef(CONFIG_DT_HAS_NXP_IMX_NETC_BLK_CTRL_ENABLED eth_nxp_imx_netc_blk.c)
 endif()
 
 zephyr_library_sources_ifdef(CONFIG_DSA_NXP_IMX_NETC	dsa_nxp_imx_netc.c)