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Update Interrupt Controller driver to support Renesas RZ/A3UL, V2L #92830

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Update Interrupt Controller driver to support Renesas RZ/A3UL, V2L #92830

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0393f0c
manifest: Update commit id for hal_renesas
Jul 7, 2025
753cb23
drivers: intc: Add external interrupt support for Renesas RZ/A3UL, V2L
Jul 7, 2025
807257e
dts: renesas: Update interrupt nodes for Renesas RZ/G3S, N2L, T2M, T2L
Jul 7, 2025
711b62b
dts: renesas: Add external interrupt support for Renesas RZ/A3UL, V2L
Jul 7, 2025
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11 changes: 11 additions & 0 deletions drivers/interrupt_controller/Kconfig.renesas_rz
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Original file line number Diff line number Diff line change
Expand Up @@ -9,3 +9,14 @@ config RENESAS_RZ_EXT_IRQ
select PINCTRL
help
Renesas RZ external interrupt controller driver

if RENESAS_RZ_EXT_IRQ

config RENESAS_RZ_INTC_HAS_NMI
bool "NMI (Non Maskable Interrupt) pin"
default y
depends on SOC_SERIES_RZG3S || SOC_SERIES_RZA3UL
help
Renesas RZ interrupt controller has NMI (Non Maskable Interrupt) pin

endif
82 changes: 47 additions & 35 deletions drivers/interrupt_controller/intc_renesas_rz_ext_irq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -12,13 +12,17 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
#if defined(CONFIG_SOC_SERIES_RZG3S)
#include <instances/rzg/r_intc_irq.h>
#include <instances/rzg/r_intc_nmi.h>
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) || \
defined(CONFIG_SOC_SERIES_RZT2M)
#include <instances/rzn/r_icu.h>
#endif /* CONFIG_SOC_SERIES_* */

#if CONFIG_DT_HAS_RENESAS_RZ_INTC_ENABLED
#include "r_intc_irq.h"
#elif CONFIG_DT_HAS_RENESAS_RZ_ICU_ENABLED
#include "r_icu.h"
#endif

#if CONFIG_RENESAS_RZ_INTC_HAS_NMI
#include "r_intc_nmi.h"
#endif

#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>

Expand All @@ -37,13 +41,14 @@ struct intc_rz_ext_irq_data {
};

/* FSP interruption handlers. */
#if defined(CONFIG_SOC_SERIES_RZG3S)
void r_intc_irq_isr(void);
void r_intc_nmi_isr(void);
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) || \
defined(CONFIG_SOC_SERIES_RZT2M)
void r_icu_isr(void);
#endif /* CONFIG_SOC_SERIES_* */
#if CONFIG_DT_HAS_RENESAS_RZ_INTC_ENABLED
void r_intc_irq_isr(void *irq);
void r_intc_nmi_isr(void *irq);
#define INTC_IRQ_ISR r_intc_irq_isr
#elif CONFIG_DT_HAS_RENESAS_RZ_ICU_ENABLED
void r_icu_isr(void *irq);
#define INTC_IRQ_ISR r_icu_isr
#endif

int intc_rz_ext_irq_enable(const struct device *dev)
{
Expand Down Expand Up @@ -143,19 +148,25 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args)
}
}

static void intc_rz_ext_irq_isr_handle(const struct device *dev)
{
const struct intc_rz_ext_irq_config *config = dev->config;

INTC_IRQ_ISR((void *)config->fsp_cfg->irq);
}

#ifdef CONFIG_CPU_CORTEX_M
#define GET_IRQ_FLAGS(index) 0
#else /* Cortex-A/R */
#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags)
#endif

#define EXT_IRQ_RZ_IRQ_CONNECT(index, isr, isr_nmi) \
#define EXT_IRQ_RZ_IRQ_CONNECT(index, isr) \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(index, 0, irq), DT_INST_IRQ_BY_IDX(index, 0, priority), \
COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \
(isr_nmi), (isr)), NULL, GET_IRQ_FLAGS(index));
isr, DEVICE_DT_INST_GET(index), GET_IRQ_FLAGS(index))

#define INTC_RZG_EXT_IRQ_INIT(index) \
static const external_irq_cfg_t g_external_irq##index##_cfg = { \
#define INTC_RZ_EXT_IRQ_INIT(index) \
static external_irq_cfg_t g_external_irq##index##_cfg = { \
.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0), \
.filter_enable = true, \
.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1, \
Expand All @@ -164,22 +175,22 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args)
.p_extend = NULL, \
.ipl = DT_INST_IRQ_BY_IDX(index, 0, priority), \
.irq = DT_INST_IRQ_BY_IDX(index, 0, irq), \
COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \
(.channel = DT_INST_IRQ_BY_IDX(index, 0, irq)), \
(.channel = DT_INST_IRQ_BY_IDX(index, 0, irq) - 1)), \
COND_CODE_0(DT_NUM_REGS(DT_DRV_INST(index)), ( \
.channel = 0), ( \
.channel = (DT_INST_REG_ADDR(index)))), \
}; \
\
PINCTRL_DT_INST_DEFINE(index); \
\
struct intc_rz_ext_irq_config intc_rz_ext_irq_config##index = { \
.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
.fsp_cfg = (external_irq_cfg_t *)&g_external_irq##index##_cfg, \
COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), ( \
.fsp_api = &g_external_irq_on_intc_nmi), ( \
.fsp_api = &g_external_irq_on_intc_irq)), \
COND_CODE_0(DT_NUM_REGS(DT_DRV_INST(index)), ( \
.fsp_api = &g_external_irq_on_intc_nmi), ( \
.fsp_api = &g_external_irq_on_intc_irq)), \
}; \
\
COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), \
COND_CODE_0(DT_NUM_REGS(DT_DRV_INST(index)), \
(static intc_nmi_instance_ctrl_t g_external_irq##index##_ctrl;), \
(static intc_irq_instance_ctrl_t g_external_irq##index##_ctrl;)) \
\
Expand All @@ -189,16 +200,18 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args)
\
static int intc_rz_ext_irq_init_##index(const struct device *dev) \
{ \
EXT_IRQ_RZ_IRQ_CONNECT(index, r_intc_irq_isr, r_intc_nmi_isr) \
COND_CODE_0(DT_NUM_REGS(DT_DRV_INST(index)), ( \
EXT_IRQ_RZ_IRQ_CONNECT(index, r_intc_nmi_isr);), ( \
EXT_IRQ_RZ_IRQ_CONNECT(index, intc_rz_ext_irq_isr_handle);)) \
return intc_rz_ext_irq_init(dev); \
}; \
\
DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL, \
&intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index, \
PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);

#define INTC_RZTN_EXT_IRQ_INIT(index) \
static const external_irq_cfg_t g_external_irq##index##_cfg = { \
#define INTC_RZ_ICU_EXT_IRQ_INIT(index) \
static external_irq_cfg_t g_external_irq##index##_cfg = { \
.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0), \
.filter_enable = true, \
.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1, \
Expand Down Expand Up @@ -226,17 +239,16 @@ static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args)
\
static int intc_rz_ext_irq_init_##index(const struct device *dev) \
{ \
EXT_IRQ_RZ_IRQ_CONNECT(index, r_icu_isr, NULL); \
EXT_IRQ_RZ_IRQ_CONNECT(index, intc_rz_ext_irq_isr_handle); \
return intc_rz_ext_irq_init(dev); \
}; \
\
DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL, \
&intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index, \
PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);

#if defined(CONFIG_SOC_SERIES_RZG3S)
DT_INST_FOREACH_STATUS_OKAY(INTC_RZG_EXT_IRQ_INIT)
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) || \
defined(CONFIG_SOC_SERIES_RZT2M)
DT_INST_FOREACH_STATUS_OKAY(INTC_RZTN_EXT_IRQ_INIT)
#if CONFIG_DT_HAS_RENESAS_RZ_INTC_ENABLED
DT_INST_FOREACH_STATUS_OKAY(INTC_RZ_EXT_IRQ_INIT)
#elif CONFIG_DT_HAS_RENESAS_RZ_ICU_ENABLED
DT_INST_FOREACH_STATUS_OKAY(INTC_RZ_ICU_EXT_IRQ_INIT)
#endif
39 changes: 28 additions & 11 deletions dts/arm/renesas/rz/rzg/r9a08g045.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -832,9 +832,11 @@
};
};

intc: interrupt-controller@41060000 {
reg = <0x41060000 0x18>;
#address-cells = <0>;
intc: intc@41060000 {
compatible = "renesas,rz-intc";
reg = <0x41060000 DT_SIZE_K(64)>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&nvic>;

nmi: nmi {
Expand All @@ -845,57 +847,72 @@
status = "disabled";
};

irq0: irq0 {
irq0: irq@0 {
compatible = "renesas,rz-ext-irq";
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1 1>;
status = "disabled";
};
irq1: irq1 {

irq1: irq@1 {
compatible = "renesas,rz-ext-irq";
reg = <0x1>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2 1>;
status = "disabled";
};
irq2: irq2 {

irq2: irq@2 {
compatible = "renesas,rz-ext-irq";
reg = <0x2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3 1>;
status = "disabled";
};
irq3: irq3 {

irq3: irq@3 {
compatible = "renesas,rz-ext-irq";
reg = <0x3>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <4 1>;
status = "disabled";
};
irq4: irq4 {

irq4: irq@4 {
compatible = "renesas,rz-ext-irq";
reg = <0x4>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <5 1>;
status = "disabled";
};
irq5: irq5 {

irq5: irq@5 {
compatible = "renesas,rz-ext-irq";
reg = <0x5>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <6 1>;
status = "disabled";
};
irq6: irq6 {

irq6: irq@6 {
compatible = "renesas,rz-ext-irq";
reg = <0x6>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <7 1>;
status = "disabled";
};
irq7: irq7 {

irq7: irq@7 {
compatible = "renesas,rz-ext-irq";
reg = <0x7>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <8 1>;
Expand Down
1 change: 1 addition & 0 deletions dts/arm/renesas/rz/rzn/r9a07g084.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,7 @@
};

icu: icu@81048000 {
compatible = "renesas,rz-icu";
reg = <0x81048000 0x1000>;
interrupt-parent = <&gic>;
#address-cells = <1>;
Expand Down
1 change: 1 addition & 0 deletions dts/arm/renesas/rz/rzt/r9a07g074.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@
};

icu: icu@81048000 {
compatible = "renesas,rz-icu";
reg = <0x81048000 0x1000>;
interrupt-parent = <&gic>;
#address-cells = <1>;
Expand Down
1 change: 1 addition & 0 deletions dts/arm/renesas/rz/rzt/r9a07g075.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -96,6 +96,7 @@
};

icu: icu@81048000 {
compatible = "renesas,rz-icu";
reg = <0x81048000 0x1000>;
interrupt-parent = <&gic>;
#address-cells = <1>;
Expand Down
80 changes: 80 additions & 0 deletions dts/arm/renesas/rz/rzv/r9a07g054.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -539,6 +539,86 @@
interrupt-names = "eri", "bri", "rxi", "txi", "tei";
status = "disabled";
};

intc: intc@410b0000 {
compatible = "renesas,rz-intc";
reg = <0x410b0000 DT_SIZE_K(64)>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&nvic>;

irq0: irq@0 {
compatible = "renesas,rz-ext-irq";
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1 1>;
status = "disabled";
};

irq1: irq@1 {
compatible = "renesas,rz-ext-irq";
reg = <0x1>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2 1>;
status = "disabled";
};

irq2: irq@2 {
compatible = "renesas,rz-ext-irq";
reg = <0x2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3 1>;
status = "disabled";
};

irq3: irq@3 {
compatible = "renesas,rz-ext-irq";
reg = <0x3>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <4 1>;
status = "disabled";
};

irq4: irq@4 {
compatible = "renesas,rz-ext-irq";
reg = <0x4>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <5 1>;
status = "disabled";
};

irq5: irq@5 {
compatible = "renesas,rz-ext-irq";
reg = <0x5>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <6 1>;
status = "disabled";
};

irq6: irq@6 {
compatible = "renesas,rz-ext-irq";
reg = <0x6>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <7 1>;
status = "disabled";
};

irq7: irq@7 {
compatible = "renesas,rz-ext-irq";
reg = <0x7>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <8 1>;
status = "disabled";
};
};
};
};

Expand Down
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