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dts: arm: microchip: mec: Add MEC5 HAL based GIRQ information #91715

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158 changes: 117 additions & 41 deletions dts/arm/microchip/mec/mec5.dtsi

Large diffs are not rendered by default.

25 changes: 0 additions & 25 deletions dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi

This file was deleted.

29 changes: 28 additions & 1 deletion dts/arm/microchip/mec/mec5_mec1743qlj.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -23,11 +23,38 @@
#include "mec5/mec5_gpspi_v2.dtsi"
#include "mec5/mec5_eeprom_8kb.dtsi"
#include "mec5/mec5_pkg176_pwms.dtsi"
#include "mec5/mec5_pkg176_uarts.dtsi"

ps2_1: ps2@40009040 {
reg = <0x40009040 0x40>;
interrupts = <101 3>;
girqs = <18 11>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
girqs = <21 25>;
status = "disabled";
};

uart2: uart@400f2c00 {
reg = <0x400f2c00 0x400>;
interrupts = <183 2>;
girqs = <15 25>;
clock-frequency = <1843200>;
current-speed = <115200>;
status = "disabled";
};

uart3: uart@400f3000 {
reg = <0x400f3000 0x400>;
interrupts = <184 2>;
girqs = <15 26>;
clock-frequency = <1843200>;
current-speed = <115200>;
status = "disabled";
};
};
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15 changes: 13 additions & 2 deletions dts/arm/microchip/mec/mec5_mec1743qsz.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -23,17 +23,28 @@
#include "mec5/mec5_gpspi_v2.dtsi"
#include "mec5/mec5_eeprom_8kb.dtsi"

ps2_1: ps2@40009040 {
reg = <0x40009040 0x40>;
interrupts = <101 3>;
girqs = <18 11>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
girqs = <21 25>;
status = "disabled";
};

uart2: uart@400f2c00 {
reg = <0x400f2c00 0x400>;
interrupts = <183 1>;
interrupts = <183 2>;
girqs = <15 25>;
clock-frequency = <1843200>;
current-speed = <38400>;
current-speed = <115200>;
status = "disabled";
};
};
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27 changes: 26 additions & 1 deletion dts/arm/microchip/mec/mec5_mec1753qlj.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -23,14 +23,39 @@
#include "mec5/mec5_eeprom_8kb.dtsi"
#include "mec5/mec5_gpspi_v2.dtsi"
#include "mec5/mec5_pkg176_pwms.dtsi"
#include "mec5/mec5_pkg176_uarts.dtsi"
#include "mec5/mec5_i3c.dtsi"

ps2_1: ps2@40009040 {
reg = <0x40009040 0x40>;
interrupts = <101 3>;
girqs = <18 11>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
status = "disabled";
};

uart2: uart@400f2c00 {
reg = <0x400f2c00 0x400>;
interrupts = <183 2>;
girqs = <15 25>;
clock-frequency = <1843200>;
current-speed = <115200>;
status = "disabled";
};

uart3: uart@400f3000 {
reg = <0x400f3000 0x400>;
interrupts = <184 2>;
girqs = <15 26>;
clock-frequency = <1843200>;
current-speed = <115200>;
status = "disabled";
};
};
};
15 changes: 13 additions & 2 deletions dts/arm/microchip/mec/mec5_mec1753qsz.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -24,17 +24,28 @@
#include "mec5/mec5_gpspi_v2.dtsi"
#include "mec5/mec5_i3c.dtsi"

ps2_1: ps2@40009040 {
reg = <0x40009040 0x40>;
interrupts = <101 3>;
girqs = <18 11>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
girqs = <21 25>;
status = "disabled";
};

uart2: uart@400f2c00 {
reg = <0x400f2c00 0x400>;
interrupts = <183 1>;
interrupts = <183 2>;
girqs = <15 25>;
clock-frequency = <1843200>;
current-speed = <38400>;
current-speed = <115200>;
status = "disabled";
};
};
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1 change: 1 addition & 0 deletions dts/arm/microchip/mec/mec5_mech1723nlj.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@
kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
girqs = <21 25>;
status = "disabled";
};
};
Expand Down
1 change: 1 addition & 0 deletions dts/arm/microchip/mec/mec5_mech1723nsz.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
kscan0: kscan@40009c00 {
reg = <0x40009c00 0x18>;
interrupts = <135 0>;
girqs = <21 25>;
status = "disabled";
};
};
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2 changes: 1 addition & 1 deletion dts/bindings/gpio/microchip,mec5-gpio.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ description: Microchip MEC5 GPIO

compatible: "microchip,mec5-gpio"

include: [gpio-controller.yaml, base.yaml]
include: ["gpio-controller.yaml", "base.yaml", "microchip,dmec-ecia-girq.yaml"]

properties:
reg:
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23 changes: 23 additions & 0 deletions dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
description: Microchip DEC/MEC series External Interrupt Aggregator GIRQ

compatible: "microchip,dmec-ecia-girq"

include: base.yaml

properties:
girqs:
type: array
required: true
description: |
Many DEC/MEC periperals interrupt signals are direct capable. The signals are
connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers:
status(latched or r/w1-c), set-enable, clr-enable, and result (read-only).
The read-only result register bits are the bitwise AND of status and enable.
Direct mode routes the individual result register bits to NVIC inputs. If
direct mode is disable by setting direct mode bit to 0 in the EC subsystem
interrupt control register then the result register outputs are OR'd together
and the OR'd result is connected to an NVIC input based on GIRQ number.
To enable an interrupt a driver must know:
a. NVIC input number and priority from the interrupts property
b. GIRQ number and bit position from the girqs property
The number of entries in interrupts and girqs should be the same in a DT node.
2 changes: 1 addition & 1 deletion dts/bindings/serial/microchip,mec5-uart.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ description: Microchip MEC5 UART

compatible: "microchip,mec5-uart"

include: [uart-controller.yaml, pinctrl-device.yaml]
include: [uart-controller.yaml, pinctrl-device.yaml, "microchip,dmec-ecia-girq.yaml"]

properties:
reg:
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2 changes: 1 addition & 1 deletion dts/bindings/spi/microchip,mec5-qspi.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ description: Microchip MEC5 series QSPI controller

compatible: "microchip,mec5-qspi"

include: [spi-controller.yaml, pinctrl-device.yaml]
include: ["spi-controller.yaml", "pinctrl-device.yaml", "microchip,dmec-ecia-girq.yaml"]

properties:
reg:
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2 changes: 1 addition & 1 deletion dts/bindings/timer/microchip,mec5-ktimer.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ description: |

compatible: "microchip,mec5-ktimer"

include: base.yaml
include: ["base.yaml", "microchip,dmec-ecia-girq.yaml"]

properties:
reg:
Expand Down