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drivers: add mipi_dbi_rpi_pico_pio #91350
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const char *failed_pin = NULL; | ||
int ret = 0; | ||
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mipi_dbi_pio_configure(dev); |
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check return code
switch (split_count) { | ||
case 4: | ||
SET_SM_PROGRAM(3, splits[0].pin_count + splits[1].pin_count + splits[2].pin_count) | ||
case 3: | ||
SET_SM_PROGRAM(2, splits[0].pin_count + splits[1].pin_count) | ||
case 2: | ||
SET_SM_PROGRAM(1, splits[0].pin_count) | ||
case 1: | ||
CONFIG_SM_PROGRAM(0, 0, 1, 2) | ||
/* 0: pull ifempty block side 1 [1] */ | ||
split->sm.program_instructions[0] = 0x99e0; | ||
/* 1: out pins, #pins side 0 [1] */ | ||
split->sm.program_instructions[1] = 0x7100 | split->pin_count; | ||
default: | ||
break; | ||
} |
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I'm guessing the fallthrough are intentional but please mark them as such (__fallthrough;
)
.cmd_data = GPIO_DT_SPEC_INST_GET_OR(n, dc_gpios, {}), \ | ||
.reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \ | ||
}; \ | ||
BUILD_ASSERT(DT_INST_PROP_LEN(n, data_gpios) < MIPI_DBI_MAX_DATA_BUS_WIDTH, \ |
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BUILD_ASSERT(DT_INST_PROP_LEN(n, data_gpios) < MIPI_DBI_MAX_DATA_BUS_WIDTH, \ | |
BUILD_ASSERT(DT_INST_PROP_LEN(n, data_gpios) <= MIPI_DBI_MAX_DATA_BUS_WIDTH, \ |
GPIO pins used for the parallel data bus. This must have as many entries as the bus is wide | ||
of the selected mipi-mode. |
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second sentence is very oddly worded
switch (split->sm.sm) { | ||
case 0: | ||
split->dma.config.dma_slot = | ||
data->pio == pio0 ? RPI_PICO_DMA_SLOT_PIO0_TX0 : RPI_PICO_DMA_SLOT_PIO1_TX0; |
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In the case of rp2350, there are three PIOs, so please consider supporting it if possible.
Do not use fixed commits, squash and force push. |
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Would be nice if this driver could be built in CI |
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Add mipi_dbi driver for MIPI_DBI_MODE_8080_BUS_8/9/16_BIT using PIO and DMA Signed-off-by: Christoph Schnetzler <schnetzler.christoph@gmail.com>
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Add mipi_dbi driver for MIPI_DBI_MODE_8080_BUS_8/9/16_BIT using PIO and DMA.
The implementation allows splitting the parallel data pins. Max 4 splits are possible as there are 4 state machines per PIO instance.
In general it works quite nice.

There is a topic to discuss though, how to determine the end of a transmission. For the data bytes one has to wait for the DMAs to finish, next the FIFOs have to be empty and at the end the PIOs need to be finished before pulling cs line high. Same for the CMD byte. There only one byte is transferred and one needs to wait only for the PIOs to finish.

The wait time is dependent on the clock div, the PIO instructions and the system clock. Right now a sleep is used. But this introduces quite a delay as context switching is possible.
One could adapt the PIO instructions to also toggle the cmd line but then one would need at least 2 PIO state machines, and it would add some additional clock cycles (probably not a big issue as it is really fast anyway).
Compared to mipi_dbi_bitbang it is currently still much faster. On my 320x240 display an animation is faded in with ~12fps. With the bitbang driver it reaches only ~3fps. Tested with an rp2040 at 125MHz.