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xtensa: allow flushing auto-refill DTLBs on page table swap #89425

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@dcpleung dcpleung commented May 2, 2025

This adds a new kconfig and corresponding code to allow flushing auto-refill data TLBs when page tables are swapped (e.g. during context switching). This is mainly used to avoid multi-hit TLB exception raised by certain memory access pattern. If memory is only marked for user mode access but not inside a memory domain, accessing that page in kernel mode would result in a TLB being filled with kernel ASID. When going back into user mode, access to the memory would result in another TLB being filled with the user mode ASID. Now there are two entries on the same memory page, and the multi-hit TLB exception will be raised if that memory page is accessed. This type of access is better served using memory partition and memory domain to share data. However, this type of access is not prohibited but highly discouraged. Wrapping the code in kconfig is simply because of the execution penalty as there will be unnecessary TLB refilling being done. So only enable this if necessary.

Fixes #88772

@dcpleung dcpleung force-pushed the xtensa/tlb_invalidate_on_context_switch branch from aa4f879 to cc94940 Compare May 2, 2025 19:40
This adds a new kconfig and corresponding code to allow flushing
auto-refill data TLBs when page tables are swapped (e.g. during
context switching). This is mainly used to avoid multi-hit TLB
exception raised by certain memory access pattern. If memory is
only marked for user mode access but not inside a memory domain,
accessing that page in kernel mode would result in a TLB being
filled with kernel ASID. When going back into user mode, access
to the memory would result in another TLB being filled with
the user mode ASID. Now there are two entries on the same memory
page, and the multi-hit TLB exception will be raised if that
memory page is accessed. This type of access is better served
using memory partition and memory domain to share data. However,
this type of access is not prohibited but highly discouraged.
Wrapping the code in kconfig is simply because of the execution
penalty as there will be unnecessary TLB refilling being done.
So only enable this if necessary.

Fixes zephyrproject-rtos#88772

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
@dcpleung dcpleung marked this pull request as ready for review May 2, 2025 23:06
@github-actions github-actions bot added the area: Xtensa Xtensa Architecture label May 2, 2025
@github-actions github-actions bot requested review from andyross, ceolin and nashif May 2, 2025 23:07
@kartben kartben merged commit d31ee53 into zephyrproject-rtos:main May 28, 2025
32 checks passed
@dcpleung dcpleung deleted the xtensa/tlb_invalidate_on_context_switch branch May 28, 2025 18:15
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xtensa: Shared memory between different privilege threads leads to MultiHit/LoadStorePrivilege exception
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