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drivers: pinctrl: enable the AFIO clock on the CH32V003/20x/30x #89138

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Merged
merged 1 commit into from
May 2, 2025
Merged

drivers: pinctrl: enable the AFIO clock on the CH32V003/20x/30x #89138

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13 changes: 13 additions & 0 deletions drivers/pinctrl/pinctrl_wch_20x_30x_afio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/

#define DT_DRV_COMPAT wch_20x_30x_afio

#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>

Expand Down Expand Up @@ -87,3 +90,13 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp

return 0;
}

static int pinctrl_clock_init(void)
{
const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id);

return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id);
}

SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
17 changes: 13 additions & 4 deletions drivers/pinctrl/pinctrl_wch_afio.c
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Expand Up @@ -4,6 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/

#define DT_DRV_COMPAT wch_afio

#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>

Expand All @@ -28,10 +31,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
uint32_t pcfr1 = AFIO->PCFR1;
uint8_t cfg = 0;

if (remap != 0) {
RCC->APB2PCENR |= RCC_AFIOEN;
}

if (pins->output_high || pins->output_low) {
cfg |= (pins->slew_rate + 1);
if (pins->drive_open_drain) {
Expand Down Expand Up @@ -77,3 +76,13 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp

return 0;
}

static int pinctrl_clock_init(void)
{
const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id);

return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id);
}

SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);
1 change: 1 addition & 0 deletions dts/riscv/wch/ch32v0/ch32v003.dtsi
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Expand Up @@ -77,6 +77,7 @@
reg = <0x40010000 0x10>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&rcc CH32V00X_CLOCK_AFIO>;
status = "okay";

gpioa: gpio@40010800 {
Expand Down
1 change: 1 addition & 0 deletions dts/riscv/wch/ch32v208/ch32v208.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,7 @@
reg = <0x40010000 16>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>;

gpioa: gpio@40010800 {
compatible = "wch,gpio";
Expand Down