boards: amd: Add generic APU board support for Versal Net SoC (Cortex-A78)

Introduce a generic board configuration for the APU on the Versal Net SoC,
which is based on the ARM Cortex-A78 processor.

This board setup provides a baseline environment for enabling and testing
Cortex-A78 features and peripheral integration on the APU subsystem.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>

Author: Appana Durga Kedareswara rao

boards/amd/versalnet_apu/Kconfig.versalnet_apu

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_VERSALNET_APU
+	select SOC_AMD_VERSALNET_APU

boards/amd/versalnet_apu/board.cmake

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)

boards/amd/versalnet_apu/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: versalnet_apu
+  vendor: amd
+  socs:
+  - name: amd_versalnet_apu

boards/amd/versalnet_apu/doc/index.rst

@@ -0,0 +1,74 @@
+.. zephyr:board:: versalnet_apu
+
+Overview
+********
+This configuration provides support for the APU(A78), ARM processing unit on AMD
+Versal Net SOC, it can operate as following:
+
+* Four independent A78 clusters each having 4 A78 cores
+
+This processing unit is based on an ARM Cortex-A78 CPU, it also enables the following devices:
+
+* ARM GIC v3 Interrupt Controller
+* Global Timer Counter
+* SBSA UART
+
+Hardware
+********
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+=======
+System Timer
+------------
+
+This board configuration uses a system timer tick frequency of 100 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+on-chip UART0.
+
+Memories
+--------
+
+Although Flash, DDR and OCM memory regions are defined in the DTS file,
+all the code plus data of the application will be loaded in the sram0 region,
+which points to the DDR memory. The ocm0 memory area is currently available
+for usage, although nothing is placed there by default.
+
+Known Problems or Limitations
+=============================
+
+The following platform features are unsupported:
+
+* Only the first cpu in the first cluster of the A78 subsystem is supported.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: versalnet_apu
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! versalnet_apu/amd_versalnet_apu
+
+
+References
+**********
+
+1. ARMv8‑A Architecture Reference Manual (ARM DDI 0487)
+2. Arm Cortex‑A78 Core Technical Reference Manual (Doc ID 101430)

boards/amd/versalnet_apu/support/xsdb.cfg

@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+proc load_image args  {
+	set elf_file [lindex $args 0]
+	set pdi_file [lindex $args 1]
+	set bl31_file [lindex $args 2]
+
+	if { [info exists ::env(HW_SERVER_URL)] } {
+		connect -url $::env(HW_SERVER_URL)
+	} else {
+		connect
+	}
+
+	device program $pdi_file
+	targets -set -nocase -filter {name =~ "Versal*"}
+	after 100
+	targets -set -filter {name =~ "Cortex-A78AE*0.0"}
+	rst -proc
+	after 100
+	dow -force $elf_file
+	dow -force $bl31_file
+	con
+	exit
+}
+
+load_image {*}$argv

boards/amd/versalnet_apu/versalnet_apu.dts

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm64/xilinx/versalnet_a78.dtsi>
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&cpu0 {
+	 clock-frequency = <100000000>;
+};
+
+&soc {
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x0 0x0 DT_SIZE_M(2048)>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};

boards/amd/versalnet_apu/versalnet_apu.yaml

@@ -0,0 +1,10 @@
+identifier: versalnet_apu
+name: AMD Development board for Versal NET APU
+arch: arm
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: amd

boards/amd/versalnet_apu/versalnet_apu_defconfig

@@ -0,0 +1,20 @@
+# The Zephyr build from this defconfig is expected to boot from
+# Xilinx Arm Trusted Firmware (ATF).
+# Boot Flow is: Boot PDI -> TF-A -> Zephyr
+
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_PL011=y
+
+# This should be commented in order to test at EL1 S (EL1 Secure)
+CONFIG_ARMV8_A_NS=y