Skip to content

Commit 1f69280

Browse files
author
Appana Durga Kedareswara rao
committed
soc: amd: Add initial support for Versal Net SoC APU (Cortex-A78)
Add initial support for the Versal Net SoC APU, which is based on the Arm Cortex-A78 processor. It includes basic wiring for memory regions, UART, interrupt controller, and timer. The versalnet_apu.dtsi file defines peripherals shared across the SoC, while versalnet_a78.dtsi captures peripherals private to the Cortex-A78 processor. These device trees lay the groundwork for further APU-based development on the Versal Net platform. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
1 parent 89d7ae3 commit 1f69280

File tree

8 files changed

+184
-4
lines changed

8 files changed

+184
-4
lines changed

‎dts/arm64/xilinx/versalnet_a78.dtsi

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
/*
2+
* Copyright (c) 2025, Advanced Micro Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include <mem.h>
10+
#include <arm64/armv8-a.dtsi>
11+
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12+
#include <amd/versalnet_apu.dtsi>
13+
14+
/ {
15+
model = "Versal NET APU";
16+
#address-cells = <2>;
17+
#size-cells = <2>;
18+
19+
cpus {
20+
#address-cells = <1>;
21+
#size-cells = <0>;
22+
23+
cpu0: cpu@0 {
24+
device_type = "cpu";
25+
compatible = "arm,cortex-a78";
26+
reg = <0>;
27+
enable-method = "psci";
28+
};
29+
30+
cpu100: cpu@100 {
31+
device_type = "cpu";
32+
compatible = "arm,cortex-a78";
33+
enable-method = "psci";
34+
reg = <0x100>;
35+
};
36+
37+
cpu200: cpu@200 {
38+
device_type = "cpu";
39+
compatible = "arm,cortex-a78";
40+
enable-method = "psci";
41+
reg = <0x200>;
42+
};
43+
44+
cpu300: cpu@300 {
45+
device_type = "cpu";
46+
compatible = "arm,cortex-a78";
47+
enable-method = "psci";
48+
reg = <0x300>;
49+
};
50+
};
51+
52+
psci {
53+
compatible = "arm,psci-1.1";
54+
method = "smc";
55+
};
56+
57+
arch_timer: timer {
58+
compatible = "arm,armv8-timer";
59+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
60+
<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
61+
<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
62+
<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
63+
interrupt-parent = <&gic>;
64+
};
65+
};
66+
67+
&soc {
68+
interrupt-parent = <&gic>;
69+
70+
gic: interrupt-controller@e2000000 {
71+
compatible = "arm,gic-v3", "arm,gic";
72+
reg = <0x0 0xe2000000 0x0 0x10000>,
73+
<0x0 0xe2060000 0x0 0x200000>;
74+
interrupt-controller;
75+
#interrupt-cells = <4>;
76+
#address-cells = <1>;
77+
#size-cells = <1>;
78+
};
79+
};

‎dts/vendor/amd/versalnet_apu.dtsi

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/*
2+
* Copyright (c) 2025, Advanced Micro Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/ {
8+
soc: soc {
9+
#address-cells = <2>;
10+
#size-cells = <2>;
11+
12+
/*
13+
* OCM (On-Chip Memory) is used by TF-A (Trusted Firmware-A) by default.
14+
* Enable this node only if TF-A is not using this memory region or if
15+
* explicit coordination is established between TF-A and Zephyr.
16+
*/
17+
ocm: memory@bbf00000 {
18+
compatible = "zephyr,memory-region";
19+
reg = <0x0 0xbbf00000 0x0 DT_SIZE_M(1)>;
20+
status = "disabled";
21+
zephyr,memory-region = "OCM";
22+
};
23+
24+
uart0: uart@f1920000 {
25+
compatible = "arm,sbsa-uart";
26+
reg = <0x0 0xf1920000 0x0 0x4c>;
27+
status = "disabled";
28+
interrupt-names = "irq_0";
29+
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
30+
};
31+
32+
uart1: uart@f1930000 {
33+
compatible = "arm,sbsa-uart";
34+
reg = <0x0 0xf1930000 0x0 0x1000>;
35+
status = "disabled";
36+
interrupt-names = "irq_1";
37+
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
38+
};
39+
};
40+
};

‎soc/xlnx/versalnet/CMakeLists.txt

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,16 +4,22 @@
44
# SPDX-License-Identifier: Apache-2.0
55
#
66

7-
zephyr_sources(
8-
soc.c
9-
)
107
zephyr_sources_ifdef(
118
CONFIG_ARM_MPU
129
arm_mpu_regions.c
10+
soc.c
11+
)
12+
zephyr_sources_ifdef(
13+
CONFIG_ARM_MMU
14+
arm_mmu_regions.c
1315
)
1416

1517
zephyr_include_directories(.)
1618

1719
if(CONFIG_SOC_AMD_VERSALNET_RPU)
1820
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
1921
endif()
22+
23+
if(CONFIG_SOC_AMD_VERSALNET_APU)
24+
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
25+
endif()

‎soc/xlnx/versalnet/Kconfig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,9 @@ config SOC_AMD_VERSALNET_RPU
1313
select GIC_SINGLE_SECURITY_STATE
1414
select CPU_HAS_ARM_MPU
1515
select ARM_MPU
16+
17+
config SOC_AMD_VERSALNET_APU
18+
select ARM64
19+
select ARM_ARCH_TIMER
20+
select CPU_CORTEX_A78
21+
select CPU_HAS_MMU

‎soc/xlnx/versalnet/Kconfig.defconfig

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,4 +22,19 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
2222

2323
endif # SOC_AMD_VERSALNET_RPU
2424

25+
if SOC_AMD_VERSALNET_APU
26+
27+
CONFIG_CACHE_MANAGEMENT=y
28+
CONFIG_ARM_ARCH_TIMER=y
29+
CONFIG_CACHE_MANAGEMENT=y
30+
31+
config NUM_IRQS
32+
# must be >= the highest interrupt number used
33+
# - include the UART interrupts
34+
default 256
35+
36+
config SYS_CLOCK_HW_CYCLES_PER_SEC
37+
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
38+
39+
endif # SOC_AMD_VERSALNET_APU
2540
endif # SOC_AMD_VERSALNET

‎soc/xlnx/versalnet/Kconfig.soc

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,17 @@ config SOC_AMD_VERSALNET_RPU
1111
bool
1212
select SOC_AMD_VERSALNET
1313
help
14-
AMD Versal NET SoC
14+
AMD Versal NET SoC RPU
15+
16+
config SOC_AMD_VERSALNET_APU
17+
bool
18+
select SOC_AMD_VERSALNET
19+
help
20+
AMD Versal NET SoC APU
1521

1622
config SOC_FAMILY
1723
default "amd_versalnet" if SOC_AMD_VERSALNET
1824

1925
config SOC
2026
default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU
27+
default "amd_versalnet_apu" if SOC_AMD_VERSALNET_APU

‎soc/xlnx/versalnet/arm_mmu_regions.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
/*
2+
* Copyright (c) 2025 Advanced Micro Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/arch/arm64/arm_mmu.h>
8+
#include <zephyr/devicetree.h>
9+
#include <zephyr/sys/util.h>
10+
11+
static const struct arm_mmu_region mmu_regions[] = {
12+
MMU_REGION_FLAT_ENTRY("GIC",
13+
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
14+
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
15+
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
16+
17+
MMU_REGION_FLAT_ENTRY("GIC",
18+
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
19+
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
20+
MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
21+
};
22+
23+
const struct arm_mmu_config mmu_config = {
24+
.num_regions = ARRAY_SIZE(mmu_regions),
25+
.mmu_regions = mmu_regions,
26+
};

‎soc/xlnx/versalnet/soc.yml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,3 +2,4 @@ family:
22
- name: amd_versalnet
33
socs:
44
- name: amd_versalnet_rpu
5+
- name: amd_versalnet_apu

0 commit comments

Comments
 (0)