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soc: arm: microchip: add common mec_gpio.h
add common mec_gpio.h to allow access to common gpio_regs structure for both mec15xx and mec17xx, used in pinctrl driver Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
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‎drivers/pinctrl/pinctrl_mchp_xec.c

Lines changed: 1 addition & 136 deletions
Original file line numberDiff line numberDiff line change
@@ -10,142 +10,7 @@
1010
#define DT_DRV_COMPAT microchip_xec_pinctrl
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1212
#include <zephyr/drivers/pinctrl.h>
13-
14-
/** @brief All GPIO register as arrays of registers */
15-
struct gpio_regs {
16-
volatile uint32_t CTRL[174];
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uint32_t RESERVED[18];
18-
volatile uint32_t PARIN[6];
19-
uint32_t RESERVED1[26];
20-
volatile uint32_t PAROUT[6];
21-
uint32_t RESERVED2[20];
22-
volatile uint32_t LOCK[6];
23-
uint32_t RESERVED3[64];
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volatile uint32_t CTRL2[174];
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};
26-
27-
#define NUM_MCHP_GPIO_PORTS 6u
28-
29-
/* GPIO Control register field definitions. */
30-
31-
/* bits[1:0] internal pull up/down selection */
32-
#define MCHP_GPIO_CTRL_PUD_POS 0
33-
#define MCHP_GPIO_CTRL_PUD_MASK0 0x03u
34-
#define MCHP_GPIO_CTRL_PUD_MASK 0x03u
35-
#define MCHP_GPIO_CTRL_PUD_NONE 0x00u
36-
#define MCHP_GPIO_CTRL_PUD_PU 0x01u
37-
#define MCHP_GPIO_CTRL_PUD_PD 0x02u
38-
/* Repeater(keeper) mode */
39-
#define MCHP_GPIO_CTRL_PUD_RPT 0x03u
40-
41-
/* bits[3:2] power gating */
42-
#define MCHP_GPIO_CTRL_PWRG_POS 2
43-
#define MCHP_GPIO_CTRL_PWRG_MASK0 0x03u
44-
#define MCHP_GPIO_CTRL_PWRG_VTR_IO 0
45-
#define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS)
46-
#define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS)
47-
#define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
48-
#define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS)
49-
50-
/* bit[8] output buffer type: push-pull or open-drain */
51-
#define MCHP_GPIO_CTRL_BUFT_POS 8
52-
#define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS)
53-
#define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS)
54-
#define MCHP_GPIO_CTRL_BUFT_PUSHPULL 0
55-
56-
/* bit[9] direction */
57-
#define MCHP_GPIO_CTRL_DIR_POS 9
58-
#define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS)
59-
#define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS)
60-
#define MCHP_GPIO_CTRL_DIR_INPUT 0
61-
62-
/*
63-
* bit[10] Alternate output disable. Default==0(alternate output enabled)
64-
* GPIO output value is controlled by bit[16] of this register.
65-
* Set bit[10]=1 if you wish to control pin output using the parallel
66-
* GPIO output register bit for this pin.
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*/
68-
#define MCHP_GPIO_CTRL_AOD_POS 10
69-
#define MCHP_GPIO_CTRL_AOD_MASK BIT(MCHP_GPIO_CTRL_AOD_POS)
70-
#define MCHP_GPIO_CTRL_AOD_DIS BIT(MCHP_GPIO_CTRL_AOD_POS)
71-
72-
/* bit[11] GPIO function output polarity */
73-
#define MCHP_GPIO_CTRL_POL_POS 11
74-
#define MCHP_GPIO_CTRL_POL_INVERT BIT(MCHP_GPIO_CTRL_POL_POS)
75-
76-
/* bits[14:12] pin mux (function) */
77-
#define MCHP_GPIO_CTRL_MUX_POS 12
78-
#define MCHP_GPIO_CTRL_MUX_MASK0 0x07u
79-
#define MCHP_GPIO_CTRL_MUX_MASK SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
80-
#define MCHP_GPIO_CTRL_MUX_F0 0
81-
#define MCHP_GPIO_CTRL_MUX_GPIO MCHP_GPIO_CTRL_MUX_F0
82-
#define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1, MCHP_GPIO_CTRL_MUX_POS)
83-
#define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2, MCHP_GPIO_CTRL_MUX_POS)
84-
#define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3, MCHP_GPIO_CTRL_MUX_POS)
85-
#define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4, MCHP_GPIO_CTRL_MUX_POS)
86-
#define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5, MCHP_GPIO_CTRL_MUX_POS)
87-
#define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6, MCHP_GPIO_CTRL_MUX_POS)
88-
#define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS)
89-
#define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS)
90-
91-
/*
92-
* bit[15] Disables input pad leaving output pad enabled
93-
* Useful for reducing power consumption of output only pins.
94-
*/
95-
#define MCHP_GPIO_CTRL_INPAD_DIS_POS 15
96-
#define MCHP_GPIO_CTRL_INPAD_DIS_MASK BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)
97-
#define MCHP_GPIO_CTRL_INPAD_DIS BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)
98-
99-
/* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */
100-
#define MCHP_GPIO_CTRL_OUTVAL_POS 16
101-
#define MCHP_GPIO_CTRL_OUTV_HI BIT(MCHP_GPIO_CTRL_OUTVAL_POS)
102-
103-
/* bit[24] Input pad value. Always live unless input pad is powered down */
104-
#define MCHP_GPIO_CTRL_INPAD_VAL_POS 24
105-
#define MCHP_GPIO_CTRL_INPAD_VAL_HI BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)
106-
107-
#define MCHP_GPIO_CTRL_DRIVE_OD_HI \
108-
(MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT + \
109-
MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTV_HI)
110-
111-
/*
112-
* Each GPIO pin implements a second control register.
113-
* GPIO Control 2 register selects pin drive strength and slew rate.
114-
* bit[0] = slew rate: 0=slow, 1=fast
115-
* bits[5:4] = drive strength
116-
* 00b = 2mA (default)
117-
* 01b = 4mA
118-
* 10b = 8mA
119-
* 11b = 12mA
120-
*/
121-
#define MCHP_GPIO_CTRL2_OFFSET 0x0500u
122-
#define MCHP_GPIO_CTRL2_SLEW_POS 0
123-
#define MCHP_GPIO_CTRL2_SLEW_MASK 0x01u
124-
#define MCHP_GPIO_CTRL2_SLEW_SLOW 0
125-
#define MCHP_GPIO_CTRL2_SLEW_FAST BIT(MCHP_GPIO_CTRL2_SLEW_POS)
126-
#define MCHP_GPIO_CTRL2_DRV_STR_POS 4
127-
#define MCHP_GPIO_CTRL2_DRV_STR_MASK 0x30u
128-
#define MCHP_GPIO_CTRL2_DRV_STR_2MA 0
129-
#define MCHP_GPIO_CTRL2_DRV_STR_4MA 0x10u
130-
#define MCHP_GPIO_CTRL2_DRV_STR_8MA 0x20u
131-
#define MCHP_GPIO_CTRL2_DRV_STR_12MA 0x30u
132-
133-
#define MCHP_XEC_NO_PULL 0x0
134-
#define MCHP_XEC_PULL_UP 0x1
135-
#define MCHP_XEC_PULL_DOWN 0x2
136-
#define MCHP_XEC_REPEATER 0x3
137-
#define MCHP_XEC_PUSH_PULL 0x0
138-
#define MCHP_XEC_OPEN_DRAIN 0x1
139-
#define MCHP_XEC_NO_OVAL 0x0
140-
#define MCHP_XEC_OVAL_LOW 0x1
141-
#define MCHP_XEC_OVAL_HIGH 0x2
142-
#define MCHP_XEC_DRVSTR_NONE 0x0
143-
#define MCHP_XEC_DRVSTR_2MA 0x1
144-
#define MCHP_XEC_DRVSTR_4MA 0x2
145-
#define MCHP_XEC_DRVSTR_8MA 0x3
146-
#define MCHP_XEC_DRVSTR_12MA 0x4
147-
148-
#define SHLU32(v, n) ((uint32_t)(v) << (n))
13+
#include <soc.h>
14914

15015
/* Microchip XEC: each GPIO pin has two 32-bit control register.
15116
* The first 32-bit register contains all pin features except

‎soc/arm/microchip_mec/common/reg/mec_gpio.h

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
/*
2+
* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef _MEC_GPIO_H
8+
#define _MEC_GPIO_H
9+
10+
#include <stdint.h>
11+
#include <stddef.h>
12+
13+
/** @brief All GPIO register as arrays of registers */
14+
struct gpio_regs {
15+
volatile uint32_t CTRL[174];
16+
uint32_t RESERVED[18];
17+
volatile uint32_t PARIN[6];
18+
uint32_t RESERVED1[26];
19+
volatile uint32_t PAROUT[6];
20+
uint32_t RESERVED2[20];
21+
volatile uint32_t LOCK[6];
22+
uint32_t RESERVED3[64];
23+
volatile uint32_t CTRL2[174];
24+
};
25+
26+
#endif /* #ifndef _MEC_GPIO_H */

‎soc/arm/microchip_mec/mec1501/soc.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,16 @@
1414
#include "MEC1501hsz.h"
1515
#include "regaccess.h"
1616

17+
/* common SoC API */
1718
#include "../common/soc_dt.h"
1819
#include "../common/soc_gpio.h"
1920
#include "../common/soc_pins.h"
2021
#include "../common/soc_espi_channels.h"
2122
#include "../common/soc_espi_saf.h"
2223

24+
/* common peripheral register defines */
25+
#include "../common/reg/mec_gpio.h"
26+
2327
#endif
2428

2529
#endif

‎soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -393,19 +393,6 @@ enum mchp_gpio_drv_str {
393393
MCHP_GPIO_DRV_STR_12MA,
394394
};
395395

396-
/** @brief All GPIO register as arrays of registers */
397-
struct gpio_regs {
398-
volatile uint32_t CTRL[174];
399-
uint32_t RESERVED[18];
400-
volatile uint32_t PARIN[6];
401-
uint32_t RESERVED1[26];
402-
volatile uint32_t PAROUT[6];
403-
uint32_t RESERVED2[20];
404-
volatile uint32_t LOCK[6];
405-
uint32_t RESERVED3[64];
406-
volatile uint32_t CTRL2[174];
407-
};
408-
409396
/** @brief GPIO control registers by pin name */
410397
struct gpio_ctrl_regs {
411398
volatile uint32_t CTRL_0000;

‎soc/arm/microchip_mec/mec172x/soc.h

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Original file line numberDiff line numberDiff line change
@@ -274,6 +274,7 @@ typedef enum {
274274
#include "../common/reg/mec_uart.h"
275275
#include "../common/reg/mec_vci.h"
276276
#include "../common/reg/mec_wdt.h"
277+
#include "../common/reg/mec_gpio.h"
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278279
/* common SoC API */
279280
#include "../common/soc_dt.h"

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