dts: riscv: Add reg-names to machine timer nodes

This commit updates all relevant device tree source files using the
riscv,machine-timer binding to explicitly define `reg-names` for the MTIME
and MTIMECMP registers.

This change ensures compatibility with the updated riscv_machine_timer
driver, which now relies on `reg-names` to resolve register addresses
instead of using fixed index positions.

Signed-off-by: Chen Xingyu <hi@xingrz.me>

Author: xingrz

dts/riscv/andes/andes_v5_ae350.dtsi

@@ -217,6 +217,7 @@
 		mtimer: timer@e6000000 {
 			compatible = "riscv,machine-timer";
 			reg = <0xe6000000 0x8 0xe6000008 0x8>;
+			reg-names = "mtime", "mtimecmp";
 			interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
 					       &cpu2_intc 7 &cpu3_intc 7
 					       &cpu4_intc 7 &cpu5_intc 7

dts/riscv/gd/gd32vf103.dtsi

@@ -43,6 +43,7 @@
 		systimer: timer@d1000000 {
 			compatible = "nuclei,systimer", "riscv,machine-timer";
 			reg = <0xd1000000 0x8 0xd1000008 0x8>;
+			reg-names = "mtime", "mtimecmp";
 			interrupts-extended = <&eclic 7 0>;
 			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
 		};