drivers: timer: riscv_machine_timer: Use reg-names to access registers

This commit updates the riscv_machine_timer driver to resolve MTIME and
MTIMECMP register addresses by their `reg-names` instead of relying on
index order.

This improves clarity and robustness in DTS bindings, and is a prerequisite
for handling cases where not both MTIME and MTIMECMP registers are present
or accessible.

Signed-off-by: Chen Xingyu <hi@xingrz.me>

Author: xingrz

drivers/timer/riscv_machine_timer.c

@@ -16,8 +16,8 @@
 
 #define DT_DRV_COMPAT riscv_machine_timer
 
-#define MTIME_REG    DT_INST_REG_ADDR_BY_IDX(0, 0)
-#define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
+#define MTIME_REG    DT_INST_REG_ADDR_BY_NAME(0, mtime)
+#define MTIMECMP_REG DT_INST_REG_ADDR_BY_NAME(0, mtimecmp)
 #define TIMER_IRQN   DT_INST_IRQN(0)
 
 #define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)

dts/bindings/timer/riscv,machine-timer.yaml

@@ -10,5 +10,7 @@ include: base.yaml
 properties:
   reg:
     required: true
+  reg-names:
+    required: true
   interrupts-extended:
     required: true