soc: xlnx: zynq7000: enable control register access

Enable access to the registers used to set a GEM instance's
TX clock frequency.

Without this memory mapping, the GEM controllers are only usable
without PHY management via MDIO with a fixed TX clock frequency
set by the FSBL. If MDIO and PHY management are enabled for
either GEM on the Zynq, the system will crash with a data abort
without this mapping.

The ZynqMP is not affected by this issue, as even with the MPU
enabled, the relevant SLCR register space is covered by the
"peripherals" mapping entry in the ZynqMP's MPU region table.

Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>

Author: ibirnbaum

soc/xlnx/zynq7000/xc7zxxx/soc.c

@@ -39,6 +39,12 @@ static const struct arm_mmu_region mmu_regions[] = {
 	/* ARM Arch timer, GIC are covered by the MPCore mapping */
 
 /* GEMs */
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
+	MMU_REGION_FLAT_ENTRY("slcr",
+			      0xF8000000,
+			      0x1000,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+#endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
 	MMU_REGION_FLAT_ENTRY("gem0",
 			      DT_REG_ADDR(DT_NODELABEL(gem0)),

soc/xlnx/zynq7000/xc7zxxxs/soc.c

@@ -39,6 +39,12 @@ static const struct arm_mmu_region mmu_regions[] = {
 	/* ARM Arch timer, GIC are covered by the MPCore mapping */
 
 /* GEMs */
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem1))
+	MMU_REGION_FLAT_ENTRY("slcr",
+			      0xF8000000,
+			      0x1000,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+#endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gem0))
 	MMU_REGION_FLAT_ENTRY("gem0",
 			      DT_REG_ADDR(DT_NODELABEL(gem0)),