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drivers: mdio: add MDIO driver for Xilinx GEM
Separate the MDIO functionality from the Xilinx GEM MAC driver into a separate driver conforming with the standard MDIO API. Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
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‎drivers/mdio/CMakeLists.txt

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@@ -20,3 +20,4 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_RENESAS_RA mdio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_LAN865X mdio_lan865x.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_SENSRY_SY1XX mdio_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_XILINX_AXI_ENET mdio_xilinx_axienet.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_XLNX_GEM mdio_xlnx_gem.c)

‎drivers/mdio/Kconfig

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@@ -41,6 +41,7 @@ source "drivers/mdio/Kconfig.renesas_ra"
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source "drivers/mdio/Kconfig.lan865x"
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source "drivers/mdio/Kconfig.sy1xx"
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source "drivers/mdio/Kconfig.xilinx_axienet"
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source "drivers/mdio/Kconfig.xlnx_gem"
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config MDIO_INIT_PRIORITY
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int "Init priority"

‎drivers/mdio/Kconfig.xlnx_gem

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# Copyright (c) 2025 Immo Birnbaum
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# SPDX-License-Identifier: Apache-2.0
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config MDIO_XLNX_GEM
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bool "Xilinx GEM MDIO controller driver"
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default y
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depends on DT_HAS_XLNX_GEM_MDIO_ENABLED
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help
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Enable Xilinx GEM MDIO support.
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if MDIO_XLNX_GEM
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config MDIO_XLNX_GEM_MAX_POLL_RETRIES
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int "Poll MDIO transaction completion max. retries"
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default 10
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help
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The number of times the completion of an MDIO
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transaction is polled before it is considered
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timed out.
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config MDIO_XLNX_GEM_POLL_DELAY
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int "Poll MDIO transaction completion delay"
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default 50
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help
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Delay in microseconds between two MDIO transaction
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completion polling operations.
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endif # MDIO_XLNX_GEM

‎drivers/mdio/mdio_xlnx_gem.c

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/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* Copyright (c) 2025 Immo Birnbaum
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(xlnx_gem_mdio, CONFIG_MDIO_LOG_LEVEL);
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#define DT_DRV_COMPAT xlnx_gem_mdio
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/*
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* Subset of register offsets and control bits / masks required for MDIO:
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*
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* Register offsets within the respective GEM's address space:
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* NWCTRL = gem.net_ctrl Network Control register
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* NWCFG = gem.net_cfg Network Configuration register
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* NWSR = gem.net_status Network Status register
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* PHYMNTNC = gem.phy_maint PHY maintenance register
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*
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* gem.net_ctrl:
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* [04] Enable MDIO port
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* gem.net_cfg:
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* [20 .. 18] MDC clock division setting
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* gem.net_status:
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* [02] PHY management idle bit
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* [01] MDIO input status
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* gem.phy_maint:
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* [31 .. 30] constant values
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* [17 .. 16] constant values
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* [29] Read operation control bit
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* [28] Write operation control bit
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* [27 .. 23] PHY address
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* [22 .. 18] Register address
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* [15 .. 00] 16-bit data word
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*/
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#define ETH_XLNX_GEM_NWCTRL_OFFSET 0x00000000
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#define ETH_XLNX_GEM_NWCTRL_MDEN_BIT BIT(4)
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#define ETH_XLNX_GEM_NWCFG_OFFSET 0x00000004
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#define ETH_XLNX_GEM_NWCFG_MDC_MASK 0x7
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#define ETH_XLNX_GEM_NWCFG_MDC_SHIFT 18
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#define ETH_XLNX_GEM_NWSR_OFFSET 0x00000008
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#define ETH_XLNX_GEM_NWSR_MDIO_IDLE_BIT BIT(2)
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#define ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET 0x00000034
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#define ETH_XLNX_GEM_PHY_MAINT_CONST_BITS 0x40020000
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#define ETH_XLNX_GEM_PHY_MAINT_READ_OP_BIT BIT(29)
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#define ETH_XLNX_GEM_PHY_MAINT_WRITE_OP_BIT BIT(28)
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#define ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK 0x0000001F
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#define ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_SHIFT 23
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#define ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK 0x0000001F
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#define ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_SHIFT 18
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#define ETH_XLNX_GEM_PHY_MAINT_DATA_MASK 0x0000FFFF
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/**
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* @brief MDC clock divider configuration enumeration type.
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*
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* Enumeration type containing the supported clock divider values
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* used to generate the MDIO interface clock (MDC) from either the
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* cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (ZynqMP).
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* This is a configuration item in the controller's net_cfg register.
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*/
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enum eth_xlnx_mdc_clock_divider {
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MDC_DIVIDER_8 = 0,
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MDC_DIVIDER_16,
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MDC_DIVIDER_32,
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MDC_DIVIDER_48,
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MDC_DIVIDER_64,
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MDC_DIVIDER_96,
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MDC_DIVIDER_128,
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MDC_DIVIDER_224
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};
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/**
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* @brief Constant device configuration data structure.
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*
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* This struct contains all device configuration data for a GEM
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* MDIO interface instance which is constant.
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*/
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struct xlnx_gem_mdio_config {
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uint32_t gem_base_addr;
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};
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/**
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* @brief GEM MDIO interface data read function
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*
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* @param dev Pointer to the GEM MDIO device
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* @param prtad MDIO address of the PHY to be accessed
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* @param regad Index of the PHY register to be read
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* @param data Read data output pointer
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* @return 0 in case of success, -ETIMEDOUT if the read operation
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* timed out (idle bit not set as expected)
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*/
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static int xlnx_gem_mdio_read(const struct device *dev, uint8_t prtad, uint8_t regad,
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uint16_t *data)
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{
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const struct xlnx_gem_mdio_config *const dev_conf = dev->config;
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uint32_t reg_val;
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uint32_t poll_cnt = 0;
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/*
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* MDIO read operation as described in Zynq-7000 TRM,
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* chapter 16.3.4, p. 517.
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*/
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/*
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* Wait until gem.net_status[phy_mgmt_idle] == 1 before issuing the
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* current command.
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*/
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do {
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if (poll_cnt++ > 0) {
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k_busy_wait(CONFIG_MDIO_XLNX_GEM_POLL_DELAY);
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}
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_NWSR_MDIO_IDLE_BIT) == 0 &&
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poll_cnt < CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES);
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if (poll_cnt == CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES) {
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LOG_ERR("%s: read from PHY address %hhu, register address %hhu timed out",
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dev->name, prtad, regad);
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return -ETIMEDOUT;
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}
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/* Assemble & write the read command to the gem.phy_maint register */
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/* Set the bits constant for any operation */
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reg_val = ETH_XLNX_GEM_PHY_MAINT_CONST_BITS;
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/* Indicate a read operation */
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reg_val |= ETH_XLNX_GEM_PHY_MAINT_READ_OP_BIT;
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/* PHY address */
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reg_val |= (((uint32_t)prtad & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK)
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<< ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_SHIFT);
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/* Register address */
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reg_val |= (((uint32_t)regad & ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK)
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<< ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_SHIFT);
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sys_write32(reg_val, dev_conf->gem_base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET);
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/*
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* Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command
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* completed.
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*/
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poll_cnt = 0;
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do {
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if (poll_cnt++ > 0) {
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k_busy_wait(CONFIG_MDIO_XLNX_GEM_POLL_DELAY);
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}
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_NWSR_MDIO_IDLE_BIT) == 0 &&
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poll_cnt < CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES);
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if (poll_cnt == CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES) {
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LOG_ERR("%s: read from PHY address %hhu, register address %hhu timed out",
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dev->name, prtad, regad);
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return -ETIMEDOUT;
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}
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/*
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* Read the data returned by the PHY -> lower 16 bits of the PHY main-
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* tenance register
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*/
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET);
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*data = (uint16_t)reg_val;
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return 0;
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}
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/**
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* @brief GEM MDIO interface data write function
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*
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* @param dev Pointer to the GEM MDIO device
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* @param prtad MDIO address of the PHY to be accessed
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* @param regad Index of the PHY register to write to
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* @param data Data word to be written to the target register
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* @return 0 in case of success, -ETIMEDOUT if the read operation
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* timed out (idle bit not set as expected)
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*/
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static int xlnx_gem_mdio_write(const struct device *dev, uint8_t prtad, uint8_t regad,
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uint16_t data)
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{
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const struct xlnx_gem_mdio_config *const dev_conf = dev->config;
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uint32_t reg_val;
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uint32_t poll_cnt = 0;
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/*
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* MDIO write operation as described in Zynq-7000 TRM,
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* chapter 16.3.4, p. 517.
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*/
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/*
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* Wait until gem.net_status[phy_mgmt_idle] == 1 before issuing the
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* current command.
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*/
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do {
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if (poll_cnt++ > 0) {
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k_busy_wait(CONFIG_MDIO_XLNX_GEM_POLL_DELAY);
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}
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_NWSR_MDIO_IDLE_BIT) == 0 &&
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poll_cnt < CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES);
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if (poll_cnt == CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES) {
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LOG_ERR("%s: write to PHY address %hhu, register address %hhu timed out", dev->name,
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prtad, regad);
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return -ETIMEDOUT;
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}
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/* Assemble & write the read command to the gem.phy_maint register */
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/* Set the bits constant for any operation */
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reg_val = ETH_XLNX_GEM_PHY_MAINT_CONST_BITS;
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/* Indicate a read operation */
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reg_val |= ETH_XLNX_GEM_PHY_MAINT_WRITE_OP_BIT;
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/* PHY address */
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reg_val |= (((uint32_t)prtad & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK)
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<< ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_SHIFT);
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/* Register address */
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reg_val |= (((uint32_t)regad & ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_MASK)
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<< ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_SHIFT);
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/* 16 bits of data for the destination register */
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reg_val |= ((uint32_t)data & ETH_XLNX_GEM_PHY_MAINT_DATA_MASK);
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sys_write32(reg_val, dev_conf->gem_base_addr + ETH_XLNX_GEM_PHY_MAINTENANCE_OFFSET);
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/*
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* Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command
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* completed.
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*/
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poll_cnt = 0;
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do {
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if (poll_cnt++ > 0) {
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k_busy_wait(CONFIG_MDIO_XLNX_GEM_POLL_DELAY);
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}
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWSR_OFFSET);
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} while ((reg_val & ETH_XLNX_GEM_NWSR_MDIO_IDLE_BIT) == 0 &&
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poll_cnt < CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES);
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if (poll_cnt == CONFIG_MDIO_XLNX_GEM_MAX_POLL_RETRIES) {
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LOG_ERR("%s: write to PHY address %hhu, register address %hhu timed out", dev->name,
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prtad, regad);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* @brief GEM MDIO interface initialization function
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* Configures the MDC clock divider in the associated GEM instance's
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* net_config (NWCFG) register and sets the MDIO enable bit in the
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* net_control (NWCTRL) register.
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*
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* @param dev Pointer to the GEM MDIO device
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* @return always returns 0
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*/
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static int xlnx_gem_mdio_initialize(const struct device *dev)
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{
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const struct xlnx_gem_mdio_config *const dev_conf = dev->config;
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uint32_t reg_val;
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uint32_t mdc_divider = (uint32_t)MDC_DIVIDER_224;
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/* Set the MDC divider in gem.net_config */
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWCFG_OFFSET);
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reg_val &= ~(ETH_XLNX_GEM_NWCFG_MDC_MASK << ETH_XLNX_GEM_NWCFG_MDC_SHIFT);
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reg_val |= ((mdc_divider & ETH_XLNX_GEM_NWCFG_MDC_MASK) << ETH_XLNX_GEM_NWCFG_MDC_SHIFT);
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sys_write32(reg_val, dev_conf->gem_base_addr + ETH_XLNX_GEM_NWCFG_OFFSET);
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/* Enable the MDIO interface */
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reg_val = sys_read32(dev_conf->gem_base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);
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reg_val |= ETH_XLNX_GEM_NWCTRL_MDEN_BIT;
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sys_write32(reg_val, dev_conf->gem_base_addr + ETH_XLNX_GEM_NWCTRL_OFFSET);
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LOG_DBG("%s: initialized", dev->name);
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return 0;
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}
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static DEVICE_API(mdio, xlnx_gem_mdio_api) = {
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.read = xlnx_gem_mdio_read,
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.write = xlnx_gem_mdio_write,
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};
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#define XLNX_GEM_MDIO_DEV_CONFIG(port) \
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static const struct xlnx_gem_mdio_config xlnx_gem##port##_mdio_cfg = { \
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.gem_base_addr = DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0), \
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};
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#define XLNX_GEM_MDIO_DEV_INIT(port) \
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DEVICE_DT_INST_DEFINE(port, &xlnx_gem_mdio_initialize, NULL, NULL, \
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&xlnx_gem##port##_mdio_cfg, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
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&xlnx_gem_mdio_api);
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#define XLNX_GEM_MDIO_INITIALIZE(port) \
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XLNX_GEM_MDIO_DEV_CONFIG(port); \
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XLNX_GEM_MDIO_DEV_INIT(port);
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DT_INST_FOREACH_STATUS_OKAY(XLNX_GEM_MDIO_INITIALIZE)

‎dts/bindings/mdio/xlnx,gem-mdio.yaml

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# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG
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# Copyright (c) 2025 Immo Birnbaum
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# SPDX-License-Identifier: Apache-2.0
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description: Xilinx GEM MDIO node
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compatible: "xlnx,gem-mdio"
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include: mdio-controller.yaml

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