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boards: qemu: add board definition for the or1k architecture
Qemu includes support for the OpenRISC 1000 CPU architecture. This patch adds a Zephyr virtual board definition which enables usage of this feature. The board definition closely mirrors the Qemu MIPS Malta board definition. Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
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‎MAINTAINERS.yml

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- jhol
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files:
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- arch/openrisc/
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- boards/qemu/or1k/
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- drivers/timer/*openrisc*
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- include/zephyr/arch/openrisc/
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- soc/qemu/or1k/

‎boards/qemu/or1k/Kconfig

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#
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# Copyright (c) 2025 Joel Holdsworth <jholdsworth@nvidia.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_QEMU_OR1K
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select QEMU_TARGET

‎boards/qemu/or1k/Kconfig.defconfig

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#
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# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if BOARD_QEMU_OR1K
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config BUILD_OUTPUT_BIN
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default n
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config QEMU_ICOUNT_SHIFT
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default 6 if QEMU_ICOUNT
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endif # BOARD_QEMU_OR1K

‎boards/qemu/or1k/Kconfig.qemu_or1k

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#
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# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_QEMU_OR1K
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select SOC_QEMU_OR1K

‎boards/qemu/or1k/board.cmake

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# SPDX-License-Identifier: Apache-2.0
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set(SUPPORTED_EMU_PLATFORMS qemu)
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set(QEMU_binary_suffix or1k)
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set(QEMU_CPU_TYPE_${ARCH} or1k)
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set(QEMU_FLAGS_${ARCH}
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-machine or1k-sim
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-nographic
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)
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board_set_debugger_ifnset(qemu)

‎boards/qemu/or1k/board.yml

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board:
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name: qemu_or1k
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full_name: QEMU Emulation for OpenRISC 1000
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vendor: qemu
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socs:
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- name: qemu_or1k

‎boards/qemu/or1k/doc/index.rst

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.. _qemu_or1k:
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OpenRISC 1000 Emulation (QEMU)
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##############################
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Overview
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********
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This board configuration will use QEMU to emulate the OpenRISC 1000 platform.
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This configuration provides support for an or1k CPU core and these devices:
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* OpenRISC Interrupt Controller
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* OpenRISC Tick Timer
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* NS16550 UART
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.. note::
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This board configuration makes no claims about its suitability for use
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with an actual OpenRISC 1000 hardware system, or any other hardware system.
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Hardware
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********
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Supported Features
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==================
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The following hardware features are supported:
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+--------------------------------+------------+----------------------+
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| Interface | Controller | Driver/Component |
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+================================+============+======================+
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| OpenRISC Interrupt Controller | on-chip | interrupt controller |
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+--------------------------------+------------+----------------------+
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| OpenRISC Tick Timer | on-chip | system clock |
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+--------------------------------+------------+----------------------+
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| NS16550 UART | FPGA | serial port |
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+--------------------------------+------------+----------------------+
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The kernel currently does not support other hardware features on this platform.
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Devices
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========
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System Clock
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------------
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Qemu Tick Timer timer uses a clock frequency of 20 MHz,
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see hw/openrisc/cputimer.c in Qemu source tree for details.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel
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with UART3.
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Programming and Debugging
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*************************
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Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
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emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: qemu_or1k
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:goals: run
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This will build an image with the synchronization sample app, boot it using
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QEMU, and display the following console output:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-v3.5.0-3843-g5a1358a9ef ***
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thread_a: Hello World from cpu 0 on qemu_or1k!
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thread_b: Hello World from cpu 0 on qemu_or1k!
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thread_a: Hello World from cpu 0 on qemu_or1k!
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thread_b: Hello World from cpu 0 on qemu_or1k!
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thread_a: Hello World from cpu 0 on qemu_or1k!
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thread_b: Hello World from cpu 0 on qemu_or1k!
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thread_a: Hello World from cpu 0 on qemu_or1k!
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thread_b: Hello World from cpu 0 on qemu_or1k!
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thread_a: Hello World from cpu 0 on qemu_or1k!
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thread_b: Hello World from cpu 0 on qemu_or1k!
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Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`.
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References
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**********
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https://www.qemu.org/

‎boards/qemu/or1k/qemu_or1k.dts

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/*
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* 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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/ {
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model = "Qemu OpenRISC 1000";
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compatible = "opencores,or1ksim";
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interrupt-parent = <&pic>;
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &uart3;
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zephyr,shell-uart = &uart3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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pic: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "opencores,or1k-pic-level";
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interrupt-controller;
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};
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};
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};
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sram0: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00000000 0x08000000>;
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};
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uart3: serial@90000300 {
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compatible = "ns16550";
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reg = <0x90000300 0x100>;
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reg-shift = <0>;
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interrupts = <2>;
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/* no matter for emulated port */
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clock-frequency = <20000000>;
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current-speed = <115200>;
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status = "okay";
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};
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};

‎boards/qemu/or1k/qemu_or1k.yaml

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identifier: qemu_or1k
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name: QEMU emulation for OpenRISC 1000
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type: qemu
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simulation:
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- name: qemu
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arch: openrisc
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toolchain:
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- zephyr
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- cross-compile
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ram: 128
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testing:
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default: true
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ignore_tags:
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- net
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- bluetooth
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vendor: qemu

‎boards/qemu/or1k/qemu_or1k_defconfig

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_OPENRISC_TICK_TIMER=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_STACK_SENTINEL=y

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