soc: qemu: Added qemu_or1k simulated SoC

Qemu includes support for the OpenRISC 1000 CPU architecture. This patch
adds a Zephyr SoC definition which enables usage of this feature.

The SoC definition closely mirrors the Qemu MIPS Malta SoC definition.

Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>

Author: jhol

MAINTAINERS.yml

@@ -5578,6 +5578,7 @@ OpenRISC Arch:
     - arch/openrisc/
     - drivers/timer/*openrisc*
     - include/zephyr/arch/openrisc/
+    - soc/qemu/or1k/
   labels:
     - "area: OpenRISC"
   tests:

soc/qemu/or1k/CMakeLists.txt

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_compile_options(
+  ${TOOLCHAIN_C_FLAGS}
+)
+
+zephyr_ld_options(
+  ${TOOLCHAIN_LD_FLAGS}
+)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/openrisc/linker.ld CACHE INTERNAL "")

soc/qemu/or1k/Kconfig

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_QEMU_OR1K
+	select OPENRISC

soc/qemu/or1k/Kconfig.defconfig

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_QEMU_OR1K
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config NUM_IRQS
+	default 32
+
+endif # SOC_QEMU_OR1K

soc/qemu/or1k/Kconfig.soc

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_QEMU_OR1K
+	bool
+
+config SOC
+	default "qemu_or1k" if SOC_QEMU_OR1K

soc/qemu/or1k/soc.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __QEMU_OR1K_SOC_H__
+#define __QEMU_OR1K_SOC_H__
+
+#endif /* __QEMU_OR1K_SOC_H__ */

soc/qemu/or1k/soc.yml

@@ -0,0 +1,2 @@
+socs:
+  - name: qemu_or1k