Skip to content

Commit 9f3e8b6

Browse files
mstasiaknordickartben
authored andcommitted
snippets: add nRF54L20pdk FLPR core snippet
Add snippet to boot nRF54L20pdk FLPR from application core. Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
1 parent 1f72cd5 commit 9f3e8b6

File tree

2 files changed

+42
-0
lines changed

2 files changed

+42
-0
lines changed

snippets/nordic-flpr/snippet.yml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,3 +9,6 @@ boards:
99
/.*/nrf54h20/cpuapp/:
1010
append:
1111
EXTRA_DTC_OVERLAY_FILE: soc/nrf54h20_cpuapp.overlay
12+
/.*/nrf54l20/cpuapp/:
13+
append:
14+
EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay
Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
/*
2+
* Copyright (c) 2025 Nordic Semiconductor
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/ {
7+
soc {
8+
reserved-memory {
9+
#address-cells = <1>;
10+
#size-cells = <1>;
11+
12+
cpuflpr_code_partition: image@1ed000 {
13+
/* FLPR core code partition */
14+
reg = <0x1ed000 DT_SIZE_K(64)>;
15+
};
16+
};
17+
18+
cpuflpr_sram_code_data: memory@2006fc00 {
19+
compatible = "mmio-sram";
20+
reg = <0x2006fc00 DT_SIZE_K(64)>;
21+
#address-cells = <1>;
22+
#size-cells = <1>;
23+
ranges = <0x0 0x2006fc00 0x10000>;
24+
};
25+
};
26+
};
27+
28+
&uart30 {
29+
status = "reserved";
30+
};
31+
32+
&cpuflpr_vpr {
33+
execution-memory = <&cpuflpr_sram_code_data>;
34+
source-memory = <&cpuflpr_code_partition>;
35+
};
36+
37+
&cpuapp_vevif_tx {
38+
status = "okay";
39+
};

0 commit comments

Comments
 (0)