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boards: nordic: add FLPR core to nRF54L20pdk
Added support for FLPR core in nRF54L20pdk board. Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
1 parent 6ad4d92 commit 1f72cd5

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-6
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boards/nordic/nrf54l20pdk/Kconfig.nrf54l20pdk

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config BOARD_NRF54L20PDK
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select SOC_NRF54L20_ENGA_CPUAPP if BOARD_NRF54L20PDK_NRF54L20_CPUAPP
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select SOC_NRF54L20_ENGA_CPUFLPR if BOARD_NRF54L20PDK_NRF54L20_CPUFLPR

boards/nordic/nrf54l20pdk/board.cmake

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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if(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP)
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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elseif(CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR)
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board_runner_args(jlink "--speed=4000")
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endif()
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf54l20pdk/doc/index.rst

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:ref:`build_an_application` and :ref:`application_run` for more details on
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building and running.
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Applications for the ``nrf54l20pdk/nrf54l20/cpuflpr`` board target need
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to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
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Enter the following command to compile ``hello_world`` for the FLPR core::
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west build -p -b nrf54l20pdk/nrf54l20/cpuflpr --sysbuild
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Flashing
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========
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boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi

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status = "okay";
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};
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&hfpll {
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/* For now use 64 MHz clock for CPU and fast peripherals. */
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clock-frequency = <DT_FREQ_M(64)>;
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-common.dtsi

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pinctrl-1 = <&pwm20_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&uart30 {
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current-speed = <115200>;
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pinctrl-0 = <&uart30_default>;
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pinctrl-1 = <&uart30_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&hfpll {
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/* For now use 64 MHz clock for CPU and fast peripherals. */
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clock-frequency = <DT_FREQ_M(64)>;
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};

boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20-pinctrl.dtsi

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low-power-enable;
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};
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};
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/omit-if-no-ref/ uart30_default: uart30_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RTS, 0, 2)>;
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};
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group2 {
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psels = <NRF_PSEL(UART_RX, 0, 1)>,
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<NRF_PSEL(UART_CTS, 0, 3)>;
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bias-pull-up;
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};
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};
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/omit-if-no-ref/ uart30_sleep: uart30_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 0)>,
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<NRF_PSEL(UART_RX, 0, 1)>,
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<NRF_PSEL(UART_RTS, 0, 2)>,
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<NRF_PSEL(UART_CTS, 0, 3)>;
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low-power-enable;
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};
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};
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};
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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf54l20_enga_cpuflpr.dtsi>
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#include "nrf54l20pdk_nrf54l20-common.dtsi"
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/ {
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model = "Nordic nRF54L20 PDK nRF54L20 FLPR MCU";
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compatible = "nordic,nrf54l20pdk_nrf54l20-cpuflpr";
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chosen {
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zephyr,console = &uart30;
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zephyr,shell-uart = &uart30;
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zephyr,code-partition = &cpuflpr_code_partition;
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zephyr,flash = &cpuflpr_rram;
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zephyr,sram = &cpuflpr_sram;
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};
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};
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&cpuflpr_sram {
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status = "okay";
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};
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&cpuflpr_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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cpuflpr_code_partition: partition@0 {
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label = "image-0";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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};
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};
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&grtc {
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owned-channels = <3 4>;
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status = "okay";
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};
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&uart30 {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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identifier: nrf54l20pdk/nrf54l20/cpuflpr
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name: nRF54L20-PDK-nRF54L20-Fast-Lightweight-Peripheral-Processor
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type: mcu
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arch: riscv
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toolchain:
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- zephyr
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sysbuild: true
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ram: 64
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flash: 64
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supported:
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- counter
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- gpio
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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable GPIO
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CONFIG_GPIO=y
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CONFIG_USE_DT_CODE_PARTITION=y
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# Execute from SRAM
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CONFIG_XIP=n

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