dts: intel_adsp_ace30: merge and cleanup ace30 dtsi files

The new ace30 files structure is organized as follows:

intel_adsp_ace30.dtsi - main file for all variants
intel_adsp_ace30_ptl.dtsi - additional file for PTL variant
intel_adsp_ace30_wcl.dtsi - additional file for WCL variant

The main ace30.dtsi file contains most of the fields,
with only the differences specified in the ace30_ptl.dtsi
and ace30_wcl.dtsi files.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>

Author: abonislawski

dts/xtensa/intel/intel_adsp_ace30.dtsi

@@ -35,20 +35,6 @@
 			cpu-power-states = <&d0i3 &d3>;
 		};
 
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "cdns,tensilica-xtensa-lx7";
-			reg = <3>;
-			cpu-power-states = <&d0i3 &d3>;
-		};
-
-		cpu4: cpu@4 {
-			device_type = "cpu";
-			compatible = "cdns,tensilica-xtensa-lx7";
-			reg = <4>;
-			cpu-power-states = <&d0i3 &d3>;
-		};
-
 		power-states {
 			d0i3: idle {
 				compatible = "zephyr,power-state";
@@ -69,12 +55,6 @@
 		};
 	};
 
-	sram0: memory@a0020000 {
-		device_type = "memory";
-		compatible = "mmio-sram";
-		reg = <0xa0020000 DT_SIZE_K(4608)>;
-	};
-
 	sram0virtual: virtualmemory@a0020000 {
 		device_type = "memory";
 		compatible = "mmio-sram";
@@ -139,6 +119,11 @@
 			reg = <0x3fe80088 0x4>;
 		};
 
+		hsbcap: hsbcap@71d00 {
+			compatible = "intel,adsp-hsbcap";
+			reg = <0x71d00 0x4>;
+		};
+
 		lsbpm: lsbpm@71d80 {
 			compatible = "intel,adsp-lsbpm";
 			reg = <0x71d80 0x0008>;
@@ -441,6 +426,14 @@
 			};
 		};
 
+		mic_privacy: mic-prv@71a40  {
+			compatible = "intel,adsp-mic-privacy";
+			reg = <0x71a40  0x8000>;
+			interrupts = <29 0 0>;
+			interrupt-parent = <&ace_intc>;
+			status = "okay";
+		};
+
 		mem_window0: mem_window@70200 {
 			compatible = "intel,adsp-mem-window";
 			reg = <0x70200 0x8>;
@@ -618,7 +611,7 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			interrupts = <4 0 0>;
-			num-irqs = <28>;
+			num-irqs = <30>;
 			interrupt-parent = <&core_intc>;
 		};