intel_adsp: ace30: Bring up ACE 3.0 (WCL)

abonislawski · kartben · commit 7918839ddd11 · 2025-05-15T22:14:44.000+02:00
This commit adds definition of ACE 3.0 Wildcat Lake board

Signed-off-by: Adrian Bonislawski &lt;adrian.bonislawski@intel.com&gt;
diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp
@@ -10,3 +10,5 @@ config BOARD_INTEL_ADSP
 	select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
 	select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
 	select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
+	select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
+	select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM
diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake
@@ -1,4 +1,4 @@
-# Copyright (c) 2022-2024 Intel Corporation
+# Copyright (c) 2022-2025 Intel Corporation
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -47,4 +47,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI
 
   board_finalize_runner_args(intel_adsp)
 
+elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM)
+
+  board_set_rimage_target(wcl)
+
+  set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key")
+
+  board_finalize_runner_args(intel_adsp)
+
 endif()
diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml
@@ -17,3 +17,6 @@ boards:
           - name: 'ptl'
             variants:
               - name: 'sim'
+          - name: 'wcl'
+            variants:
+              - name: 'sim'
diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl.dts b/boards/intel/adsp/intel_adsp_ace30_wcl.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_adsp_ace30_wcl.dtsi>
+
+/ {
+	model = "intel_adsp_ace30_wcl";
+	compatible = "intel";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &mem_window3;
+	};
+};
diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+
+CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
+
+CONFIG_DCACHE_LINE_SIZE=64
diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts b/boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <intel/intel_adsp_ace30_wcl.dtsi>
+
+/ {
+	model = "intel_adsp_ace30_wcl_sim";
+	compatible = "intel";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &mem_window3;
+	};
+};
diff --git a/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_INTEL_ADSP_SIM=y
+CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=n
+
+CONFIG_BUILD_OUTPUT_BIN=n
+
+CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
+
+CONFIG_DCACHE_LINE_SIZE=64
diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml
@@ -12,6 +12,20 @@ testing:
     - bluetooth
     - mcumgr
 variants:
+  intel_adsp/ace30/wcl:
+    toolchain:
+      - xt-clang
+      - zephyr
+  intel_adsp/ace30/wcl/sim:
+    type: sim
+    simulation:
+      - name: custom
+        exec: acesim
+    toolchain:
+      - xt-clang
+      - zephyr
+    testing:
+      timeout_multiplier: 8
   intel_adsp/ace30/ptl:
     toolchain:
       - xt-clang
diff --git a/dts/xtensa/intel/intel_adsp_ace30_wcl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_wcl.dtsi
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30 b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30
diff --git a/soc/intel/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c
