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boards: silabs: Add ITM configuration
Configure pinout and frequency for Serial Wire Output to enable use of the SWO logging backend on Silicon Labs dev kits. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
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boards/silabs/dev_kits/sltb010a/Kconfig.defconfig

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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_SLTB010A
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configdefault LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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if SOC_GECKO_USE_RAIL
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config FPU
@@ -24,3 +29,5 @@ endif # BT
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config REGULATOR
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default y if SI7210
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endif

boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi

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bias-pull-up;
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};
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};
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itm_default: itm_default {
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group0 {
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pins = <GPIO_SWV_PA3>;
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drive-push-pull;
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output-high;
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};
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};
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};

boards/silabs/dev_kits/sltb010a/thunderboard.dtsi

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clock-frequency = <76800000>;
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};
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&itm {
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pinctrl-0 = <&itm_default>;
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pinctrl-names = "default";
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swo-ref-frequency = <DT_FREQ_K(76800)>;
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};
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&pstate_em3 {
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status = "disabled";
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};

boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig

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if BOARD_XG24_DK2601B
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configdefault LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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if SOC_GECKO_USE_RAIL
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config FPU

boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi

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bias-pull-up;
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};
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};
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itm_default: itm_default {
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group0 {
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pins = <GPIO_SWV_PA3>;
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drive-push-pull;
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output-high;
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};
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};
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};

boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts

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clock-frequency = <78000000>;
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};
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&itm {
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pinctrl-0 = <&itm_default>;
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pinctrl-names = "default";
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swo-ref-frequency = <DT_FREQ_M(78)>;
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};
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&hfxo {
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status = "okay";
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ctune = <140>;

boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig

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if BOARD_XG24_EK2703A
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configdefault LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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config CMU_HFXO_FREQ
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default 39000000
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boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi

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bias-pull-up;
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};
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};
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itm_default: itm_default {
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group0 {
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pins = <GPIO_SWV_PA3>;
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drive-push-pull;
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output-high;
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};
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};
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};

boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts

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clock-frequency = <78000000>;
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};
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&itm {
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pinctrl-0 = <&itm_default>;
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pinctrl-names = "default";
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swo-ref-frequency = <DT_FREQ_M(78)>;
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};
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&hfxo {
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status = "okay";
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ctune = <140>;

boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig

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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_XG27_DK2602A
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configdefault LOG_BACKEND_SWO_FREQ_HZ
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default 875000
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if SOC_GECKO_USE_RAIL
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config FPU
@@ -24,3 +29,5 @@ endif # BT
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config REGULATOR
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default y if SI7210
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endif

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