dts: arm: silabs: Add ITM node to cpu core for Series 2

ARM Cortex-M33 has the Instrumentation Trace Macrocell peripheral.
Add it to SoC DTS.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>

Author: asmellby

dts/arm/silabs/efr32bg2x.dtsi

@@ -123,6 +123,13 @@
 			 * managed by sl_power_manager on S2 devices.
 			 */
 			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {

dts/arm/silabs/efr32mg21.dtsi

@@ -109,6 +109,11 @@
 				compatible = "arm,armv8m-mpu";
 				reg = <0xe000ed90 0x40>;
 			};
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 	};
 

dts/arm/silabs/efr32mg24.dtsi

@@ -144,6 +144,13 @@
 			 * The minimum residency and exit latency is
 			 * managed by sl_power_manager on S2 devices.
 			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {

dts/arm/silabs/efr32xg23.dtsi

@@ -154,6 +154,13 @@
 			 * The minimum residency and exit latency is
 			 * managed by sl_power_manager on S2 devices.
 			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {

dts/arm/silabs/xg29/xg29.dtsi

@@ -151,6 +151,13 @@
 			 * The minimum residency and exit latency is
 			 * managed by sl_power_manager on S2 devices.
 			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {