@@ -519,22 +519,22 @@ static int adxl345_init(const struct device *dev)
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}
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#ifdef CONFIG_ADXL345_TRIGGER
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- #define ADXL345_CFG_IRQ (inst ) \
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+ #define ADXL345_CFG_IRQ (inst ) \
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.interrupt = GPIO_DT_SPEC_INST_GET(inst, int2_gpios),
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#else
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#define ADXL345_CFG_IRQ (inst )
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#endif /* CONFIG_ADXL345_TRIGGER */
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- #define ADXL345_RTIO_SPI_DEFINE (inst ) \
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- COND_CODE_1(CONFIG_SPI_RTIO, \
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- (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
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- SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
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- SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
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+ #define ADXL345_RTIO_SPI_DEFINE (inst ) \
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+ COND_CODE_1(CONFIG_SPI_RTIO, \
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+ (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
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+ SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
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+ SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
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())
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- #define ADXL345_RTIO_I2C_DEFINE (inst ) \
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- COND_CODE_1(CONFIG_I2C_RTIO, \
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- (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
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+ #define ADXL345_RTIO_I2C_DEFINE (inst ) \
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+ COND_CODE_1(CONFIG_I2C_RTIO, \
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+ (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
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())
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/** RTIO SQE/CQE pool size depends on the fifo-watermark because we
@@ -544,49 +544,49 @@ static int adxl345_init(const struct device *dev)
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* frame, and then end up calling the completion event so the
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* application receives it).
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*/
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- #define ADXL345_RTIO_DEFINE (inst ) \
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- /* Conditionally include SPI and/or I2C parts based on their presence */ \
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- COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
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- (ADXL345_RTIO_SPI_DEFINE(inst)), \
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- ()) \
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- COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
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- (ADXL345_RTIO_I2C_DEFINE(inst)), \
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- ()) \
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+ #define ADXL345_RTIO_DEFINE (inst ) \
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+ /* Conditionally include SPI and/or I2C parts based on their presence */ \
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+ COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
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+ (ADXL345_RTIO_SPI_DEFINE(inst)), \
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+ ()) \
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+ COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
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+ (ADXL345_RTIO_I2C_DEFINE(inst)), \
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+ ()) \
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RTIO_DEFINE(adxl345_rtio_ctx_##inst, \
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2 * DT_INST_PROP(inst, fifo_watermark) + 2, \
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2 * DT_INST_PROP(inst, fifo_watermark) + 2);
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- #define ADXL345_CONFIG (inst ) \
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- .odr = DT_INST_PROP(inst, odr), \
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- .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
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- .fifo_config.fifo_trigger = ADXL345_INT2, \
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+ #define ADXL345_CONFIG (inst ) \
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+ .odr = DT_INST_PROP(inst, odr), \
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+ .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
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+ .fifo_config.fifo_trigger = ADXL345_INT2, \
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.fifo_config.fifo_samples = DT_INST_PROP_OR(inst, fifo_watermark, 0),
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- #define ADXL345_CONFIG_SPI (inst ) \
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- { \
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- .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \
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- SPI_WORD_SET(8) | \
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- SPI_TRANSFER_MSB | \
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- SPI_MODE_CPOL | \
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- SPI_MODE_CPHA, \
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- 0)}, \
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- .bus_is_ready = adxl345_bus_is_ready_spi, \
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- .reg_access = adxl345_reg_access_spi, \
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- .bus_type = ADXL345_BUS_SPI, \
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- ADXL345_CONFIG(inst) \
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- COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
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- (ADXL345_CFG_IRQ(inst)), ()) \
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+ #define ADXL345_CONFIG_SPI (inst ) \
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+ { \
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+ .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \
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+ SPI_WORD_SET(8) | \
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+ SPI_TRANSFER_MSB | \
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+ SPI_MODE_CPOL | \
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+ SPI_MODE_CPHA, \
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+ 0)}, \
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+ .bus_is_ready = adxl345_bus_is_ready_spi, \
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+ .reg_access = adxl345_reg_access_spi, \
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+ .bus_type = ADXL345_BUS_SPI, \
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+ ADXL345_CONFIG(inst) \
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+ COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
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+ (ADXL345_CFG_IRQ(inst)), ()) \
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}
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- #define ADXL345_CONFIG_I2C (inst ) \
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- { \
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- .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
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- .bus_is_ready = adxl345_bus_is_ready_i2c, \
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- .reg_access = adxl345_reg_access_i2c, \
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- .bus_type = ADXL345_BUS_I2C, \
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- ADXL345_CONFIG(inst) \
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- COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
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- (ADXL345_CFG_IRQ(inst)), ()) \
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+ #define ADXL345_CONFIG_I2C (inst ) \
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+ { \
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+ .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
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+ .bus_is_ready = adxl345_bus_is_ready_i2c, \
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+ .reg_access = adxl345_reg_access_i2c, \
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+ .bus_type = ADXL345_BUS_I2C, \
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+ ADXL345_CONFIG(inst) \
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+ COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
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+ (ADXL345_CFG_IRQ(inst)), ()) \
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}
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#define ADXL345_DEFINE (inst ) \
@@ -602,17 +602,17 @@ static int adxl345_init(const struct device *dev)
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"fifo-watermark must be between 1 and 32. Please set it in " \
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"the device-tree node properties"); \
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\
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- IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
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- static struct adxl345_dev_data adxl345_data_##inst = { \
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- IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
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- .iodev = &adxl345_iodev_##inst,)) \
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- }; \
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- static const struct adxl345_dev_config adxl345_config_##inst = \
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- COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
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- (ADXL345_CONFIG_I2C(inst))); \
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- \
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- SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \
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- &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL,\
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- CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); \
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+ IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
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+ static struct adxl345_dev_data adxl345_data_##inst = { \
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+ IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
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+ .iodev = &adxl345_iodev_##inst,)) \
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+ }; \
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+ static const struct adxl345_dev_config adxl345_config_##inst = \
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+ COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
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+ (ADXL345_CONFIG_I2C(inst))); \
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+ \
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+ SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \
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+ &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL, \
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+ CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs);
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DT_INST_FOREACH_STATUS_OKAY (ADXL345_DEFINE )
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