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drivers: spi: litex: remove core_ prefix
remove `core_` prefix from code and register names, got dropped in litex in enjoy-digital/litex#2253 Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2 files changed

+52
-52
lines changed

2 files changed

+52
-52
lines changed

drivers/spi/spi_litex_litespi.c

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,12 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
1818

1919
#define SPI_LITEX_HAS_IRQ (SPI_LITEX_ALL_HAS_IRQ || dev_config->has_irq)
2020

21-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0x0
22-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
23-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 0x2
21+
#define SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET 0x0
22+
#define SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
23+
#define SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET 0x2
2424

25-
#define SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0x0
26-
#define SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 0x1
25+
#define SPIFLASH_MASTER_STATUS_TX_READY_OFFSET 0x0
26+
#define SPIFLASH_MASTER_STATUS_RX_READY_OFFSET 0x1
2727

2828
#define SPI_MAX_WORD_SIZE 32
2929
#define SPI_MAX_CS_SIZE 4
@@ -32,18 +32,18 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
3232
#define SPI_LITEX_MASK BIT(0)
3333

3434
struct spi_litex_dev_config {
35-
uint32_t core_master_cs_addr;
36-
uint32_t core_master_phyconfig_addr;
37-
uint32_t core_master_rxtx_addr;
38-
uint32_t core_master_rxtx_size;
39-
uint32_t core_master_status_addr;
35+
uint32_t master_cs_addr;
36+
uint32_t master_phyconfig_addr;
37+
uint32_t master_rxtx_addr;
38+
uint32_t master_rxtx_size;
39+
uint32_t master_status_addr;
4040
uint32_t phy_clk_divisor_addr;
4141
bool phy_clk_divisor_exists;
4242
#if SPI_LITEX_ANY_HAS_IRQ
4343
bool has_irq;
4444
void (*irq_config_func)(const struct device *dev);
45-
uint32_t core_master_ev_pending_addr;
46-
uint32_t core_master_ev_enable_addr;
45+
uint32_t master_ev_pending_addr;
46+
uint32_t master_ev_enable_addr;
4747
#endif
4848
};
4949

@@ -142,12 +142,12 @@ static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t
142142
uint32_t addr)
143143
{
144144
uint32_t tmp = len & BIT_MASK(8);
145-
uint32_t word = tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET * 8);
145+
uint32_t word = tmp << (SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET * 8);
146146

147147
tmp = width & BIT_MASK(8);
148-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
148+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
149149
tmp = mask & BIT_MASK(8);
150-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET * 8);
150+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET * 8);
151151
litex_write32(word, addr);
152152
}
153153

@@ -159,10 +159,10 @@ static void spi_litex_spi_do_tx(const struct device *dev)
159159
uint8_t len;
160160
uint32_t txd = 0U;
161161

162-
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
162+
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->master_rxtx_size);
163163
if (len != data->len) {
164164
spiflash_len_mask_width_write(len * 8, SPI_LITEX_WIDTH, SPI_LITEX_MASK,
165-
dev_config->core_master_phyconfig_addr);
165+
dev_config->master_phyconfig_addr);
166166
data->len = len;
167167
}
168168

@@ -171,7 +171,7 @@ static void spi_litex_spi_do_tx(const struct device *dev)
171171
}
172172

173173
LOG_DBG("txd: 0x%x", txd);
174-
litex_write32(txd, dev_config->core_master_rxtx_addr);
174+
litex_write32(txd, dev_config->master_rxtx_addr);
175175

176176
spi_context_update_tx(ctx, data->dfs, len / data->dfs);
177177
}
@@ -183,7 +183,7 @@ static void spi_litex_spi_do_rx(const struct device *dev)
183183
struct spi_context *ctx = &data->ctx;
184184
uint32_t rxd;
185185

186-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
186+
rxd = litex_read32(dev_config->master_rxtx_addr);
187187
LOG_DBG("rxd: 0x%x", rxd);
188188

189189
if (spi_context_rx_buf_on(ctx)) {
@@ -200,24 +200,24 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
200200
struct spi_context *ctx = &data->ctx;
201201
uint32_t rxd;
202202

203-
litex_write32(BIT(config->slave), dev_config->core_master_cs_addr);
203+
litex_write32(BIT(config->slave), dev_config->master_cs_addr);
204204

205205
/* Flush RX buffer */
206-
while ((litex_read8(dev_config->core_master_status_addr) &
207-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
208-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
206+
while ((litex_read8(dev_config->master_status_addr) &
207+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
208+
rxd = litex_read32(dev_config->master_rxtx_addr);
209209
LOG_DBG("flushed rxd: 0x%x", rxd);
210210
}
211211

212-
while (!(litex_read8(dev_config->core_master_status_addr) &
213-
BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
212+
while (!(litex_read8(dev_config->master_status_addr) &
213+
BIT(SPIFLASH_MASTER_STATUS_TX_READY_OFFSET))) {
214214
;
215215
}
216216

217217
#if SPI_LITEX_ANY_HAS_IRQ
218218
if (SPI_LITEX_HAS_IRQ) {
219-
litex_write8(BIT(0), dev_config->core_master_ev_enable_addr);
220-
litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
219+
litex_write8(BIT(0), dev_config->master_ev_enable_addr);
220+
litex_write8(BIT(0), dev_config->master_ev_pending_addr);
221221

222222
spi_litex_spi_do_tx(dev);
223223

@@ -228,15 +228,15 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
228228
do {
229229
spi_litex_spi_do_tx(dev);
230230

231-
while (!(litex_read8(dev_config->core_master_status_addr) &
232-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
231+
while (!(litex_read8(dev_config->master_status_addr) &
232+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
233233
;
234234
}
235235

236236
spi_litex_spi_do_rx(dev);
237237
} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
238238

239-
litex_write32(0, dev_config->core_master_cs_addr);
239+
litex_write32(0, dev_config->master_cs_addr);
240240

241241
spi_context_complete(ctx, dev, 0);
242242

@@ -317,18 +317,18 @@ static void spi_litex_irq_handler(const struct device *dev)
317317
const struct spi_litex_dev_config *dev_config = dev->config;
318318
struct spi_context *ctx = &data->ctx;
319319

320-
if (litex_read8(dev_config->core_master_ev_pending_addr) & BIT(0)) {
320+
if (litex_read8(dev_config->master_ev_pending_addr) & BIT(0)) {
321321
spi_litex_spi_do_rx(dev);
322322

323323
/* ack reader irq */
324-
litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
324+
litex_write8(BIT(0), dev_config->master_ev_pending_addr);
325325

326326
if (spi_context_tx_on(ctx) || spi_context_rx_on(ctx)) {
327327
spi_litex_spi_do_tx(dev);
328328
} else {
329-
litex_write8(0, dev_config->core_master_ev_enable_addr);
329+
litex_write8(0, dev_config->master_ev_enable_addr);
330330

331-
litex_write32(0, dev_config->core_master_cs_addr);
331+
litex_write32(0, dev_config->master_cs_addr);
332332

333333
spi_context_complete(ctx, dev, 0);
334334
}
@@ -370,8 +370,8 @@ static DEVICE_API(spi, spi_litex_api) = {
370370
};
371371

372372
#define SPI_LITEX_IRQ(n) \
373-
BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, core_master_ev_pending) && \
374-
DT_INST_REG_HAS_NAME(n, core_master_ev_enable), "registers for interrupts missing"); \
373+
BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, master_ev_pending) && \
374+
DT_INST_REG_HAS_NAME(n, master_ev_enable), "registers for interrupts missing"); \
375375
\
376376
static void spi_litex_irq_config##n(const struct device *dev) \
377377
{ \
@@ -385,8 +385,8 @@ static DEVICE_API(spi, spi_litex_api) = {
385385
.has_irq = DT_INST_IRQ_HAS_IDX(n, 0), \
386386
.irq_config_func = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), \
387387
(spi_litex_irq_config##n), (NULL)), \
388-
.core_master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_pending, 0), \
389-
.core_master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_enable, 0),
388+
.master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_pending, 0), \
389+
.master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_enable, 0),
390390

391391
#define SPI_INIT(n) \
392392
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), (SPI_LITEX_IRQ(n))) \
@@ -396,16 +396,16 @@ static DEVICE_API(spi, spi_litex_api) = {
396396
SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
397397
}; \
398398
\
399-
static struct spi_litex_dev_config spi_litex_cfg_##n = { \
400-
.core_master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_cs), \
401-
.core_master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_phyconfig), \
402-
.core_master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_rxtx), \
403-
.core_master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, core_master_rxtx), \
404-
.core_master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_status), \
405-
.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
406-
.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
399+
static struct spi_litex_dev_config spi_litex_cfg_##n = { \
400+
.master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, master_cs), \
401+
.master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, master_phyconfig), \
402+
.master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, master_rxtx), \
403+
.master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, master_rxtx), \
404+
.master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, master_status), \
405+
.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
406+
.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
407407
IF_ENABLED(SPI_LITEX_ANY_HAS_IRQ, (SPI_LITEX_IRQ_CONFIG(n))) \
408-
}; \
408+
}; \
409409
\
410410
SPI_DEVICE_DT_INST_DEFINE(n, \
411411
spi_litex_init, NULL, &spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL, \

dts/riscv/riscv32-litex-vexriscv.dtsi

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -102,11 +102,11 @@
102102
<0xe000c010 0x4>,
103103
<0xe000c800 0x4>,
104104
<0x60000000 0x1000000>;
105-
reg-names = "core_mmap_dummy_bits",
106-
"core_master_cs",
107-
"core_master_phyconfig",
108-
"core_master_rxtx",
109-
"core_master_status",
105+
reg-names = "mmap_dummy_bits",
106+
"master_cs",
107+
"master_phyconfig",
108+
"master_rxtx",
109+
"master_status",
110110
"phy_clk_divisor",
111111
"flash_mmap";
112112
#address-cells = <1>;

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