@@ -18,12 +18,12 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
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#define SPI_LITEX_HAS_IRQ (SPI_LITEX_ALL_HAS_IRQ || dev_config->has_irq)
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- #define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0x0
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- #define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
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- #define SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 0x2
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+ #define SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET 0x0
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+ #define SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
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+ #define SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET 0x2
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- #define SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0x0
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- #define SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 0x1
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+ #define SPIFLASH_MASTER_STATUS_TX_READY_OFFSET 0x0
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+ #define SPIFLASH_MASTER_STATUS_RX_READY_OFFSET 0x1
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#define SPI_MAX_WORD_SIZE 32
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#define SPI_MAX_CS_SIZE 4
@@ -32,18 +32,18 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
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#define SPI_LITEX_MASK BIT(0)
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struct spi_litex_dev_config {
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- uint32_t core_master_cs_addr ;
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- uint32_t core_master_phyconfig_addr ;
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- uint32_t core_master_rxtx_addr ;
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- uint32_t core_master_rxtx_size ;
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- uint32_t core_master_status_addr ;
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+ uint32_t master_cs_addr ;
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+ uint32_t master_phyconfig_addr ;
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+ uint32_t master_rxtx_addr ;
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+ uint32_t master_rxtx_size ;
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+ uint32_t master_status_addr ;
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uint32_t phy_clk_divisor_addr ;
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bool phy_clk_divisor_exists ;
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#if SPI_LITEX_ANY_HAS_IRQ
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bool has_irq ;
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void (* irq_config_func )(const struct device * dev );
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- uint32_t core_master_ev_pending_addr ;
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- uint32_t core_master_ev_enable_addr ;
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+ uint32_t master_ev_pending_addr ;
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+ uint32_t master_ev_enable_addr ;
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#endif
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};
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@@ -142,12 +142,12 @@ static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t
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uint32_t addr )
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{
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uint32_t tmp = len & BIT_MASK (8 );
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- uint32_t word = tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET * 8 );
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+ uint32_t word = tmp << (SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET * 8 );
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tmp = width & BIT_MASK (8 );
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- word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET * 8 );
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+ word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET * 8 );
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tmp = mask & BIT_MASK (8 );
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- word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET * 8 );
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+ word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET * 8 );
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litex_write32 (word , addr );
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}
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@@ -159,10 +159,10 @@ static void spi_litex_spi_do_tx(const struct device *dev)
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uint8_t len ;
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uint32_t txd = 0U ;
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- len = MIN (spi_context_max_continuous_chunk (ctx ), dev_config -> core_master_rxtx_size );
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+ len = MIN (spi_context_max_continuous_chunk (ctx ), dev_config -> master_rxtx_size );
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if (len != data -> len ) {
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spiflash_len_mask_width_write (len * 8 , SPI_LITEX_WIDTH , SPI_LITEX_MASK ,
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- dev_config -> core_master_phyconfig_addr );
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+ dev_config -> master_phyconfig_addr );
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data -> len = len ;
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}
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@@ -171,7 +171,7 @@ static void spi_litex_spi_do_tx(const struct device *dev)
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}
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LOG_DBG ("txd: 0x%x" , txd );
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- litex_write32 (txd , dev_config -> core_master_rxtx_addr );
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+ litex_write32 (txd , dev_config -> master_rxtx_addr );
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spi_context_update_tx (ctx , data -> dfs , len / data -> dfs );
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}
@@ -183,7 +183,7 @@ static void spi_litex_spi_do_rx(const struct device *dev)
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struct spi_context * ctx = & data -> ctx ;
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uint32_t rxd ;
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- rxd = litex_read32 (dev_config -> core_master_rxtx_addr );
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+ rxd = litex_read32 (dev_config -> master_rxtx_addr );
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LOG_DBG ("rxd: 0x%x" , rxd );
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if (spi_context_rx_buf_on (ctx )) {
@@ -200,24 +200,24 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
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struct spi_context * ctx = & data -> ctx ;
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uint32_t rxd ;
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- litex_write32 (BIT (config -> slave ), dev_config -> core_master_cs_addr );
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+ litex_write32 (BIT (config -> slave ), dev_config -> master_cs_addr );
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/* Flush RX buffer */
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- while ((litex_read8 (dev_config -> core_master_status_addr ) &
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- BIT (SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET ))) {
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- rxd = litex_read32 (dev_config -> core_master_rxtx_addr );
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+ while ((litex_read8 (dev_config -> master_status_addr ) &
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+ BIT (SPIFLASH_MASTER_STATUS_RX_READY_OFFSET ))) {
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+ rxd = litex_read32 (dev_config -> master_rxtx_addr );
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LOG_DBG ("flushed rxd: 0x%x" , rxd );
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}
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- while (!(litex_read8 (dev_config -> core_master_status_addr ) &
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- BIT (SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET ))) {
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+ while (!(litex_read8 (dev_config -> master_status_addr ) &
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+ BIT (SPIFLASH_MASTER_STATUS_TX_READY_OFFSET ))) {
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;
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}
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#if SPI_LITEX_ANY_HAS_IRQ
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if (SPI_LITEX_HAS_IRQ ) {
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- litex_write8 (BIT (0 ), dev_config -> core_master_ev_enable_addr );
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- litex_write8 (BIT (0 ), dev_config -> core_master_ev_pending_addr );
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+ litex_write8 (BIT (0 ), dev_config -> master_ev_enable_addr );
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+ litex_write8 (BIT (0 ), dev_config -> master_ev_pending_addr );
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spi_litex_spi_do_tx (dev );
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@@ -228,15 +228,15 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
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do {
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spi_litex_spi_do_tx (dev );
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- while (!(litex_read8 (dev_config -> core_master_status_addr ) &
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- BIT (SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET ))) {
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+ while (!(litex_read8 (dev_config -> master_status_addr ) &
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+ BIT (SPIFLASH_MASTER_STATUS_RX_READY_OFFSET ))) {
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;
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}
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spi_litex_spi_do_rx (dev );
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} while (spi_context_tx_on (ctx ) || spi_context_rx_on (ctx ));
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- litex_write32 (0 , dev_config -> core_master_cs_addr );
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+ litex_write32 (0 , dev_config -> master_cs_addr );
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spi_context_complete (ctx , dev , 0 );
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@@ -317,18 +317,18 @@ static void spi_litex_irq_handler(const struct device *dev)
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const struct spi_litex_dev_config * dev_config = dev -> config ;
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struct spi_context * ctx = & data -> ctx ;
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- if (litex_read8 (dev_config -> core_master_ev_pending_addr ) & BIT (0 )) {
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+ if (litex_read8 (dev_config -> master_ev_pending_addr ) & BIT (0 )) {
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spi_litex_spi_do_rx (dev );
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/* ack reader irq */
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- litex_write8 (BIT (0 ), dev_config -> core_master_ev_pending_addr );
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+ litex_write8 (BIT (0 ), dev_config -> master_ev_pending_addr );
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if (spi_context_tx_on (ctx ) || spi_context_rx_on (ctx )) {
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spi_litex_spi_do_tx (dev );
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} else {
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- litex_write8 (0 , dev_config -> core_master_ev_enable_addr );
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+ litex_write8 (0 , dev_config -> master_ev_enable_addr );
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- litex_write32 (0 , dev_config -> core_master_cs_addr );
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+ litex_write32 (0 , dev_config -> master_cs_addr );
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spi_context_complete (ctx , dev , 0 );
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}
@@ -370,8 +370,8 @@ static DEVICE_API(spi, spi_litex_api) = {
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};
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#define SPI_LITEX_IRQ (n ) \
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- BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, core_master_ev_pending ) && \
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- DT_INST_REG_HAS_NAME(n, core_master_ev_enable ), "registers for interrupts missing"); \
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+ BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, master_ev_pending ) && \
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+ DT_INST_REG_HAS_NAME(n, master_ev_enable ), "registers for interrupts missing"); \
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\
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static void spi_litex_irq_config##n(const struct device *dev) \
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{ \
@@ -385,8 +385,8 @@ static DEVICE_API(spi, spi_litex_api) = {
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.has_irq = DT_INST_IRQ_HAS_IDX(n, 0), \
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.irq_config_func = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), \
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(spi_litex_irq_config##n), (NULL)), \
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- .core_master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_pending , 0), \
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- .core_master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_enable , 0),
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+ .master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_pending , 0), \
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+ .master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_enable , 0),
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#define SPI_INIT (n ) \
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IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), (SPI_LITEX_IRQ(n))) \
@@ -396,16 +396,16 @@ static DEVICE_API(spi, spi_litex_api) = {
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SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
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}; \
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\
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- static struct spi_litex_dev_config spi_litex_cfg_##n = { \
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- .core_master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_cs), \
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- .core_master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_phyconfig), \
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- .core_master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_rxtx), \
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- .core_master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, core_master_rxtx), \
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- .core_master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_status), \
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- .phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
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- .phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
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+ static struct spi_litex_dev_config spi_litex_cfg_##n = { \
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+ .master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, master_cs), \
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+ .master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, master_phyconfig), \
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+ .master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, master_rxtx), \
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+ .master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, master_rxtx), \
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+ .master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, master_status), \
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+ .phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
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+ .phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
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IF_ENABLED(SPI_LITEX_ANY_HAS_IRQ, (SPI_LITEX_IRQ_CONFIG(n))) \
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- }; \
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+ }; \
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\
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SPI_DEVICE_DT_INST_DEFINE(n, \
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spi_litex_init, NULL, &spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL, \
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