drivers: spi: litex: use async

implement async spi transfers

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

drivers/spi/spi_litex_litespi.c

@@ -14,6 +14,9 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
 #include "spi_litex_common.h"
 
 #define SPI_LITEX_ANY_HAS_IRQ DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
+#define SPI_LITEX_ALL_HAS_IRQ DT_ALL_INST_HAS_PROP_STATUS_OKAY(interrupts)
+
+#define SPI_LITEX_HAS_IRQ (SPI_LITEX_ALL_HAS_IRQ || dev_config->has_irq)
 
 #define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET   0x0
 #define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
@@ -25,6 +28,9 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
 #define SPI_MAX_WORD_SIZE 32
 #define SPI_MAX_CS_SIZE   4
 
+#define SPI_LITEX_WIDTH   BIT(0)
+#define SPI_LITEX_MASK    BIT(0)
+
 struct spi_litex_dev_config {
 	uint32_t core_master_cs_addr;
 	uint32_t core_master_phyconfig_addr;
@@ -35,6 +41,7 @@ struct spi_litex_dev_config {
 	bool phy_clk_divisor_exists;
 #if SPI_LITEX_ANY_HAS_IRQ
 	bool has_irq;
+	void (*irq_config_func)(const struct device *dev);
 	uint32_t core_master_ev_pending_addr;
 	uint32_t core_master_ev_enable_addr;
 #endif
@@ -43,9 +50,7 @@ struct spi_litex_dev_config {
 struct spi_litex_data {
 	struct spi_context ctx;
 	uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
-#if SPI_LITEX_ANY_HAS_IRQ
-	struct k_sem sem_rx_ready;
-#endif /* SPI_LITEX_ANY_HAS_IRQ */
+	uint8_t len; /* length of the last transfer in bytes */
 };
 
 
@@ -70,6 +75,11 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
 {
 	struct spi_litex_data *dev_data = dev->data;
 
+	if (spi_context_configured(&dev_data->ctx, config)) {
+		/* Context is already configured */
+		return 0;
+	}
+
 	if (config->slave != 0) {
 		if (config->slave >= SPI_MAX_CS_SIZE) {
 			LOG_ERR("More slaves than supported");
@@ -93,11 +103,6 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
 		return -ENOTSUP;
 	}
 
-	if (config->operation & SPI_LOCK_ON) {
-		LOG_ERR("Lock On not supported");
-		return -ENOTSUP;
-	}
-
 	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
 	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
 		LOG_ERR("Only supports single mode");
@@ -128,6 +133,8 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
 
 	spi_litex_set_frequency(dev, config);
 
+	dev_data->ctx.config = config;
+
 	return 0;
 }
 
@@ -144,40 +151,54 @@ static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t
 	litex_write32(word, addr);
 }
 
-static void spi_litex_wait_for_rx_ready(const struct device *dev)
+static void spi_litex_spi_do_tx(const struct device *dev)
 {
 	const struct spi_litex_dev_config *dev_config = dev->config;
-
-#if SPI_LITEX_ANY_HAS_IRQ
 	struct spi_litex_data *data = dev->data;
-
-	if (dev_config->has_irq) {
-		/* Wait for the RX ready event */
-		k_sem_take(&data->sem_rx_ready, K_FOREVER);
-		return;
+	struct spi_context *ctx = &data->ctx;
+	uint8_t len;
+	uint32_t txd = 0U;
+
+	len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
+	if (len != data->len) {
+		spiflash_len_mask_width_write(len * 8, SPI_LITEX_WIDTH, SPI_LITEX_MASK,
+						dev_config->core_master_phyconfig_addr);
+		data->len = len;
 	}
-#endif /* SPI_LITEX_ANY_HAS_IRQ */
 
-	while (!(litex_read8(dev_config->core_master_status_addr) &
-		 BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
-		;
+	if (spi_context_tx_buf_on(ctx)) {
+		litex_spi_tx_put(len, &txd, ctx->tx_buf);
 	}
+
+	LOG_DBG("txd: 0x%x", txd);
+	litex_write32(txd, dev_config->core_master_rxtx_addr);
+
+	spi_context_update_tx(ctx, data->dfs, len / data->dfs);
 }
 
-static int spi_litex_xfer(const struct device *dev, const struct spi_config *config)
+static void spi_litex_spi_do_rx(const struct device *dev)
 {
 	const struct spi_litex_dev_config *dev_config = dev->config;
 	struct spi_litex_data *data = dev->data;
 	struct spi_context *ctx = &data->ctx;
-	uint32_t txd, rxd;
-	int ret = 0;
+	uint32_t rxd;
+
+	rxd = litex_read32(dev_config->core_master_rxtx_addr);
+	LOG_DBG("rxd: 0x%x", rxd);
+
+	if (spi_context_rx_buf_on(ctx)) {
+		litex_spi_rx_put(data->len, &rxd, ctx->rx_buf);
+	}
 
-	uint8_t len = data->dfs; /* SPI Xfer length*/
-	uint8_t old_len = len;   /* old SPI Xfer length*/
-	uint8_t width = BIT(0);  /* SPI Xfer width*/
-	uint8_t mask = BIT(0);   /* SPI Xfer mask*/
+	spi_context_update_rx(ctx, data->dfs, data->len / data->dfs);
+}
 
-	spiflash_len_mask_width_write(len * 8, width, mask, dev_config->core_master_phyconfig_addr);
+static int spi_litex_xfer(const struct device *dev, const struct spi_config *config)
+{
+	const struct spi_litex_dev_config *dev_config = dev->config;
+	struct spi_litex_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	uint32_t rxd;
 
 	litex_write32(BIT(config->slave), dev_config->core_master_cs_addr);
 
@@ -188,100 +209,104 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
 		LOG_DBG("flushed rxd: 0x%x", rxd);
 	}
 
+	while (!(litex_read8(dev_config->core_master_status_addr) &
+			BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
+		;
+	}
+
 #if SPI_LITEX_ANY_HAS_IRQ
-	if (dev_config->has_irq) {
+	if (SPI_LITEX_HAS_IRQ) {
 		litex_write8(BIT(0), dev_config->core_master_ev_enable_addr);
 		litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
-		k_sem_reset(&data->sem_rx_ready);
+
+		spi_litex_spi_do_tx(dev);
+
+		return spi_context_wait_for_completion(ctx);
 	}
 #endif /* SPI_LITEX_ANY_HAS_IRQ */
 
 	do {
-		len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
-		if (len != old_len) {
-			spiflash_len_mask_width_write(len * 8, width, mask,
-						      dev_config->core_master_phyconfig_addr);
-			old_len = len;
-		}
-
-		if (spi_context_tx_buf_on(ctx)) {
-			litex_spi_tx_put(len, &txd, ctx->tx_buf);
-		} else {
-			txd = 0U;
-		}
+		spi_litex_spi_do_tx(dev);
 
 		while (!(litex_read8(dev_config->core_master_status_addr) &
-			 BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
+			BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
 			;
 		}
 
-		LOG_DBG("txd: 0x%x", txd);
-		litex_write32(txd, dev_config->core_master_rxtx_addr);
-
-		spi_context_update_tx(ctx, data->dfs, len / data->dfs);
-
-		spi_litex_wait_for_rx_ready(dev);
-
-		rxd = litex_read32(dev_config->core_master_rxtx_addr);
-		LOG_DBG("rxd: 0x%x", rxd);
-
-		if (spi_context_rx_buf_on(ctx)) {
-			litex_spi_rx_put(len, &rxd, ctx->rx_buf);
-		}
-
-		spi_context_update_rx(ctx, data->dfs, len / data->dfs);
-
+		spi_litex_spi_do_rx(dev);
 	} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
 
 	litex_write32(0, dev_config->core_master_cs_addr);
 
-#if SPI_LITEX_ANY_HAS_IRQ
-	if (dev_config->has_irq) {
-		/* Wait for the RX ready event */
-		litex_write8(0, dev_config->core_master_ev_enable_addr);
-	}
-#endif /* SPI_LITEX_ANY_HAS_IRQ */
 	spi_context_complete(ctx, dev, 0);
 
-	return ret;
+	return 0;
 }
 
-static int spi_litex_transceive(const struct device *dev, const struct spi_config *config,
-				const struct spi_buf_set *tx_bufs,
-				const struct spi_buf_set *rx_bufs)
+static int transceive(const struct device *dev,
+		      const struct spi_config *config,
+		      const struct spi_buf_set *tx_bufs,
+		      const struct spi_buf_set *rx_bufs,
+		      bool asynchronous,
+		      spi_callback_t cb,
+		      void *userdata)
 {
 	struct spi_litex_data *data = dev->data;
-
-	int ret = spi_config(dev, config);
-
-	if (ret) {
-		return ret;
-	}
+	int ret;
 
 	if (!tx_bufs && !rx_bufs) {
 		return 0;
 	}
 
+	spi_context_lock(&data->ctx, asynchronous, cb, userdata, config);
+
+	ret = spi_config(dev, config);
+	if (ret < 0) {
+		goto end;
+	}
+
 	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, data->dfs);
 
 	ret = spi_litex_xfer(dev, config);
 
+end:
+	spi_context_release(&data->ctx, ret);
+
 	return ret;
 }
 
+static int spi_litex_transceive(const struct device *dev,
+				const struct spi_config *config,
+				const struct spi_buf_set *tx_bufs,
+				const struct spi_buf_set *rx_bufs)
+{
+	return transceive(dev, config, tx_bufs, rx_bufs, false, NULL, NULL);
+}
+
 #ifdef CONFIG_SPI_ASYNC
-static int spi_litex_transceive_async(const struct device *dev, const struct spi_config *config,
+static int spi_litex_transceive_async(const struct device *dev,
+				      const struct spi_config *config,
 				      const struct spi_buf_set *tx_bufs,
 				      const struct spi_buf_set *rx_bufs,
-				      struct k_poll_signal *async)
+				      spi_callback_t cb,
+				      void *userdata)
 {
+#if SPI_LITEX_ANY_HAS_IRQ
+	const struct spi_litex_dev_config *dev_config = dev->config;
+
+	if (SPI_LITEX_HAS_IRQ) {
+		return transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata);
+	}
+#endif /* SPI_LITEX_ANY_HAS_IRQ */
 	return -ENOTSUP;
 }
 #endif /* CONFIG_SPI_ASYNC */
 
 static int spi_litex_release(const struct device *dev, const struct spi_config *config)
 {
+	struct spi_litex_data *data = dev->data;
 
+	spi_context_unlock_unconditionally(&data->ctx);
 	return 0;
 }
 
@@ -290,16 +315,48 @@ static void spi_litex_irq_handler(const struct device *dev)
 {
 	struct spi_litex_data *data = dev->data;
 	const struct spi_litex_dev_config *dev_config = dev->config;
+	struct spi_context *ctx = &data->ctx;
 
 	if (litex_read8(dev_config->core_master_ev_pending_addr) & BIT(0)) {
-		k_sem_give(&data->sem_rx_ready);
+		spi_litex_spi_do_rx(dev);
 
 		/* ack reader irq */
 		litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
+
+		if (spi_context_tx_on(ctx) || spi_context_rx_on(ctx)) {
+			spi_litex_spi_do_tx(dev);
+		} else {
+			litex_write8(0, dev_config->core_master_ev_enable_addr);
+
+			litex_write32(0, dev_config->core_master_cs_addr);
+
+			spi_context_complete(ctx, dev, 0);
+		}
 	}
 }
 #endif /* SPI_LITEX_ANY_HAS_IRQ */
 
+static int spi_litex_init(const struct device *dev)
+{
+	const struct spi_litex_dev_config *dev_config = dev->config;
+	struct spi_litex_data *data = dev->data;
+
+#if SPI_LITEX_ANY_HAS_IRQ
+	if (SPI_LITEX_HAS_IRQ) {
+		dev_config->irq_config_func(dev);
+	}
+#endif /* SPI_LITEX_ANY_HAS_IRQ */
+
+	data->len = dev_config->master_rxtx_size;
+
+	spiflash_len_mask_width_write(data->len * 8, SPI_LITEX_WIDTH, SPI_LITEX_MASK,
+				      dev_config->master_phyconfig_addr);
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
 /* Device Instantiation */
 static DEVICE_API(spi, spi_litex_api) = {
 	.transceive = spi_litex_transceive,
@@ -316,21 +373,18 @@ static DEVICE_API(spi, spi_litex_api) = {
 	BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, core_master_ev_pending) &&				   \
 	DT_INST_REG_HAS_NAME(n, core_master_ev_enable), "registers for interrupts missing");	   \
 												   \
-	static int spi_litex_irq_config##n(const struct device *dev)                               \
+	static void spi_litex_irq_config##n(const struct device *dev)	                           \
 	{                                                                                          \
 		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_litex_irq_handler,      \
 			    DEVICE_DT_INST_GET(n), 0);                                             \
                                                                                                    \
 		irq_enable(DT_INST_IRQN(n));                                                       \
-												   \
-		return 0;                                                                          \
 	};
 
-#define SPI_LITEX_IRQ_DATA(n)									   \
-	.sem_rx_ready = Z_SEM_INITIALIZER(spi_litex_data_##n.sem_rx_ready, 0, 1),
-
 #define SPI_LITEX_IRQ_CONFIG(n)									   \
 	.has_irq = DT_INST_IRQ_HAS_IDX(n, 0),							   \
+	.irq_config_func = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0),				   \
+					(spi_litex_irq_config##n), (NULL)),			   \
 	.core_master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_pending, 0),  \
 	.core_master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_enable, 0),
 
@@ -340,7 +394,6 @@ static DEVICE_API(spi, spi_litex_api) = {
 	static struct spi_litex_data spi_litex_data_##n = {					   \
 		SPI_CONTEXT_INIT_LOCK(spi_litex_data_##n, ctx),					   \
 		SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx),					   \
-		IF_ENABLED(SPI_LITEX_ANY_HAS_IRQ, (SPI_LITEX_IRQ_DATA(n)))			   \
 	};											   \
 												   \
 	static struct spi_litex_dev_config spi_litex_cfg_##n = {                                   \
@@ -355,8 +408,7 @@ static DEVICE_API(spi, spi_litex_api) = {
 	};                                                                                         \
 												   \
 	SPI_DEVICE_DT_INST_DEFINE(n,								   \
-		COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), (spi_litex_irq_config##n), (NULL)), NULL,   \
-		&spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,	   \
-		&spi_litex_api);
+		spi_litex_init, NULL, &spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL,	   \
+		CONFIG_SPI_INIT_PRIORITY, &spi_litex_api);
 
 DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)