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drivers: mipi_dsi: add mipi phys timing setting for renesas,ra-mipi-dsi
Add timing configuration in dts for renesas,ra-mipi-dsi Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
1 parent fadd3f8 commit 759ddf2

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3 files changed

+194
-89
lines changed

3 files changed

+194
-89
lines changed

‎boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
group1 {
1010
/* SCL1 SDA1 */
1111
psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
12-
<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
12+
<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
1313
drive-strength = "medium";
1414
};
1515
};
@@ -27,3 +27,23 @@
2727
&zephyr_lcdif {
2828
input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
2929
};
30+
31+
&mipi_dsi {
32+
status = "okay";
33+
pll-div = <1>;
34+
pll-mul-int = <50>;
35+
pll-mul-frac = "0.00";
36+
lp-divisor = <5>;
37+
ulps-wakeup-period = <97>;
38+
video-mode-delay = <186>;
39+
timing = <1183 11 26 40>;
40+
41+
phys-timing {
42+
t-init = <71999>;
43+
t-clk-prep = <8>;
44+
t-hs-prep = <5>;
45+
t-lp-exit = <7>;
46+
dphytim4 = <27 1 19 7>;
47+
dphytim5 = <19 8 11>;
48+
};
49+
};

‎drivers/mipi_dsi/dsi_renesas_ra.c

Lines changed: 95 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -15,28 +15,6 @@
1515

1616
LOG_MODULE_REGISTER(dsi_renesas_ra, CONFIG_MIPI_DSI_LOG_LEVEL);
1717

18-
/* MIPI PHY Macros */
19-
#define MIPI_PHY_CLKSTPT (1183)
20-
#define MIPI_PHY_CLKBFHT (11)
21-
#define MIPI_PHY_CLKKPT (26)
22-
#define MIPI_PHY_GOLPBKT (40)
23-
24-
#define MIPI_PHY_TINIT (71999)
25-
#define MIPI_PHY_TCLKPREP (8)
26-
#define MIPI_PHY_THSPREP (5)
27-
#define MIPI_PHY_TCLKTRAIL (7)
28-
#define MIPI_PHY_TCLKPOST (19)
29-
#define MIPI_PHY_TCLKPRE (1)
30-
#define MIPI_PHY_TCLKZERO (27)
31-
#define MIPI_PHY_THSEXIT (11)
32-
#define MIPI_PHY_THSTRAIL (8)
33-
#define MIPI_PHY_THSZERO (19)
34-
#define MIPI_PHY_TLPEXIT (7)
35-
#define LP_DIVISOR (4)
36-
#define PLL_MUL_SETTING (49)
37-
#define VIDEO_MODE_DELAY (186)
38-
#define ULPS_WAKEUP_PERIOD (97)
39-
4018
struct mipi_dsi_renesas_ra_config {
4119
const struct device *clock_dev;
4220
struct clock_control_ra_subsys_cfg clock_dsi_subsys;
@@ -246,6 +224,65 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
246224
return 0;
247225
}
248226

227+
#define RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(n) \
228+
static const mipi_phy_timing_t mipi_phy_##n##_timing = { \
229+
.t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF), \
230+
.t_clk_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), 0, 0xFF), \
231+
.t_hs_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), 0, 0xFF), \
232+
.t_lp_exit = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_lp_exit), 0, 0xFF), \
233+
.dphytim4_b = \
234+
{ \
235+
.t_clk_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
236+
dphytim4, 0), \
237+
.t_clk_pre = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
238+
dphytim4, 1), \
239+
.t_clk_post = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
240+
dphytim4, 2), \
241+
.t_clk_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
242+
dphytim4, 3), \
243+
}, \
244+
.dphytim5_b = \
245+
{ \
246+
.t_hs_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
247+
dphytim5, 0), \
248+
.t_hs_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
249+
dphytim5, 1), \
250+
.t_hs_exit = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing), \
251+
dphytim5, 2), \
252+
}, \
253+
}; \
254+
\
255+
static const mipi_phy_cfg_t mipi_phy_##n##_cfg = { \
256+
.pll_settings = \
257+
{ \
258+
.div = DT_INST_PROP(n, pll_div) - 1, \
259+
.mul_frac = DT_INST_ENUM_IDX(n, pll_mul_frac), \
260+
.mul_int = CLAMP(DT_INST_PROP(n, pll_mul_int), 20, 180) - 1, \
261+
}, \
262+
.lp_divisor = CLAMP(DT_INST_PROP(n, lp_divisor), 1, 32) - 1, \
263+
.p_timing = &mipi_phy_##n##_timing, \
264+
}; \
265+
\
266+
mipi_phy_ctrl_t mipi_phy_##n##_ctrl; \
267+
\
268+
static const mipi_phy_instance_t mipi_phy##n = { \
269+
.p_ctrl = &mipi_phy_##n##_ctrl, \
270+
.p_cfg = &mipi_phy_##n##_cfg, \
271+
.p_api = &g_mipi_phy, \
272+
};
273+
274+
#define RENESAS_RA_MIPI_DSI_PHYS_GET(n) &mipi_phy##n
275+
276+
#define RENESAS_RA_MIPI_DSI_TIMING_DEFINE(n) \
277+
static const mipi_dsi_timing_t mipi_dsi_##n##_timing = { \
278+
.clock_stop_time = DT_INST_PROP_BY_IDX(n, timing, 0), \
279+
.clock_beforehand_time = DT_INST_PROP_BY_IDX(n, timing, 1), \
280+
.clock_keep_time = DT_INST_PROP_BY_IDX(n, timing, 2), \
281+
.go_lp_and_back = DT_INST_PROP_BY_IDX(n, timing, 3), \
282+
};
283+
284+
#define RENESAS_RA_MIPI_DSI_TIMING_GET(n) &mipi_dsi_##n##_timing
285+
249286
#define RENESAS_MIPI_DSI_DEVICE(id) \
250287
static void mipi_dsi_ra_configure_func_##id(void) \
251288
{ \
@@ -256,33 +293,8 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
256293
irq_enable(DT_INST_IRQ_BY_NAME(id, sq0, irq)); \
257294
} \
258295
\
259-
mipi_phy_ctrl_t mipi_phy_##id##_ctrl; \
260-
\
261-
static const mipi_phy_timing_t mipi_phy_##id##_timing = { \
262-
.t_init = 0x3FFFF & (uint32_t)MIPI_PHY_TINIT, \
263-
.t_clk_prep = (uint8_t)MIPI_PHY_TCLKPREP, \
264-
.t_hs_prep = (uint8_t)MIPI_PHY_THSPREP, \
265-
.dphytim4_b.t_clk_trail = (uint32_t)MIPI_PHY_TCLKTRAIL, \
266-
.dphytim4_b.t_clk_post = (uint32_t)MIPI_PHY_TCLKPOST, \
267-
.dphytim4_b.t_clk_pre = (uint32_t)MIPI_PHY_TCLKPRE, \
268-
.dphytim4_b.t_clk_zero = (uint32_t)MIPI_PHY_TCLKZERO, \
269-
.dphytim5_b.t_hs_exit = (uint32_t)MIPI_PHY_THSEXIT, \
270-
.dphytim5_b.t_hs_trail = (uint32_t)MIPI_PHY_THSTRAIL, \
271-
.dphytim5_b.t_hs_zero = (uint32_t)MIPI_PHY_THSZERO, \
272-
.t_lp_exit = (uint32_t)MIPI_PHY_TLPEXIT, \
273-
}; \
274-
\
275-
static const mipi_phy_cfg_t mipi_phy_##id##_cfg = { \
276-
.pll_settings = {.div = 0, .mul_int = PLL_MUL_SETTING, .mul_frac = 0}, \
277-
.lp_divisor = LP_DIVISOR, \
278-
.p_timing = &mipi_phy_##id##_timing, \
279-
}; \
280-
\
281-
static const mipi_phy_instance_t mipi_phy##id = { \
282-
.p_ctrl = &mipi_phy_##id##_ctrl, \
283-
.p_cfg = &mipi_phy_##id##_cfg, \
284-
.p_api = &g_mipi_phy, \
285-
}; \
296+
RENESAS_RA_MIPI_DSI_TIMING_DEFINE(id) \
297+
RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(id) \
286298
\
287299
static const mipi_dsi_extended_cfg_t mipi_dsi_##id##_extended_cfg = { \
288300
.dsi_seq0.ipl = DT_INST_IRQ_BY_NAME(id, sq0, priority), \
@@ -324,51 +336,46 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
324336
R_DSILINK_SQCH1IER_RXAKE_Msk, \
325337
}; \
326338
\
327-
static const mipi_dsi_timing_t mipi_dsi_##id##_timing = { \
328-
.clock_stop_time = MIPI_PHY_CLKSTPT, \
329-
.clock_beforehand_time = MIPI_PHY_CLKBFHT, \
330-
.clock_keep_time = MIPI_PHY_CLKKPT, \
331-
.go_lp_and_back = MIPI_PHY_GOLPBKT, \
332-
}; \
333-
\
334339
static const struct mipi_dsi_renesas_ra_config ra_config_##id = { \
335340
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
336-
.clock_dsi_subsys = { \
337-
.mstp = DT_INST_CLOCKS_CELL(id, mstp), \
338-
.stop_bit = DT_INST_CLOCKS_CELL(id, stop_bit), \
339-
}, \
341+
.clock_dsi_subsys = \
342+
{ \
343+
.mstp = DT_INST_CLOCKS_CELL(id, mstp), \
344+
.stop_bit = DT_INST_CLOCKS_CELL(id, stop_bit), \
345+
}, \
340346
.irq_configure = mipi_dsi_ra_configure_func_##id, \
341347
}; \
342348
\
343349
static struct mipi_dsi_renesas_ra_data ra_data_##id = { \
344-
.mipi_dsi_cfg = { \
345-
.p_mipi_phy_instance = &mipi_phy##id, \
346-
.p_timing = &mipi_dsi_##id##_timing, \
347-
.sync_pulse = (0), \
348-
.vertical_sync_polarity = 1, \
349-
.horizontal_sync_polarity = 1, \
350-
.video_mode_delay = VIDEO_MODE_DELAY, \
351-
.hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk, \
352-
.hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk, \
353-
.hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk, \
354-
.ulps_wakeup_period = ULPS_WAKEUP_PERIOD, \
355-
.continuous_clock = (1), \
356-
.hs_tx_timeout = 0, \
357-
.lp_rx_timeout = 0, \
358-
.turnaround_timeout = 0, \
359-
.bta_timeout = 0, \
360-
.lprw_timeout = 0, \
361-
.hsrw_timeout = 0, \
362-
.max_return_packet_size = 1, \
363-
.ecc_enable = (1), \
364-
.crc_check_mask = (mipi_dsi_vc_t)(0x0), \
365-
.scramble_enable = (0), \
366-
.tearing_detect = (0), \
367-
.eotp_enable = (1), \
368-
.p_extend = &mipi_dsi_##id##_extended_cfg, \
369-
.p_callback = mipi_dsi_callback, \
370-
.p_context = DEVICE_DT_INST_GET(id), \
371-
}, \
350+
.mipi_dsi_cfg = \
351+
{ \
352+
.p_mipi_phy_instance = RENESAS_RA_MIPI_DSI_PHYS_GET(id), \
353+
.p_timing = RENESAS_RA_MIPI_DSI_TIMING_GET(id), \
354+
.sync_pulse = (0), \
355+
.vertical_sync_polarity = 1, \
356+
.horizontal_sync_polarity = 1, \
357+
.video_mode_delay = DT_INST_PROP(id, video_mode_delay), \
358+
.hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk, \
359+
.hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk, \
360+
.hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk, \
361+
.ulps_wakeup_period = DT_INST_PROP(id, ulps_wakeup_period), \
362+
.continuous_clock = (1), \
363+
.hs_tx_timeout = 0, \
364+
.lp_rx_timeout = 0, \
365+
.turnaround_timeout = 0, \
366+
.bta_timeout = 0, \
367+
.lprw_timeout = 0, \
368+
.hsrw_timeout = 0, \
369+
.max_return_packet_size = 1, \
370+
.ecc_enable = (1), \
371+
.crc_check_mask = (mipi_dsi_vc_t)(0x0), \
372+
.scramble_enable = (0), \
373+
.tearing_detect = (0), \
374+
.eotp_enable = (1), \
375+
.p_extend = &mipi_dsi_##id##_extended_cfg, \
376+
.p_callback = mipi_dsi_callback, \
377+
.p_context = DEVICE_DT_INST_GET(id), \
378+
}, \
372379
}; \
373380
\
374381
DEVICE_DT_INST_DEFINE(id, &mipi_dsi_renesas_ra_init, NULL, &ra_data_##id, &ra_config_##id, \

‎dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,3 +18,81 @@ properties:
1818
type: string-array
1919
required: true
2020
description: name of each interrupt
21+
22+
pll-div:
23+
type: int
24+
enum: [1, 2, 3, 4]
25+
description:
26+
PHY PLL divisor.
27+
28+
pll-mul-int:
29+
type: int
30+
description:
31+
PHY PLL integer multiplier.
32+
33+
pll-mul-frac:
34+
type: string
35+
enum: ["0.00", "0.33", "0.66", "0.50"]
36+
description:
37+
PHY PLL fractional multiplier.
38+
39+
lp-divisor:
40+
type: int
41+
description:
42+
PHY PLL LP speed divisor.
43+
44+
ulps-wakeup-period:
45+
type: int
46+
description: ULPS wakeup period.
47+
48+
video-mode-delay:
49+
type: int
50+
description: |
51+
Set the delay value inside DSI Host until the transfer begins.
52+
53+
timing:
54+
type: array
55+
description: |
56+
MIPI DSI timing parameter: <CLKSTPT CLKBFHT CLKKPT GOLPBKT>
57+
58+
child-binding:
59+
description: |
60+
MIPI PHY timing configuration. The child node must be named "phys-timing".
61+
Refer to '57. MIPI PHY - RA8D1 MCU group HWM' for detail parameter description.
62+
63+
properties:
64+
t-init:
65+
type: int
66+
required: true
67+
description: |
68+
Minimum duration of the TINIT state (Units: operation clock cycles).
69+
70+
t-clk-prep:
71+
type: int
72+
required: true
73+
description: |
74+
Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state).
75+
76+
t-hs-prep:
77+
type: int
78+
required: true
79+
description: |
80+
Duration of the data lane LP-00 state (immediately before entry to the HS-0 state).
81+
82+
t-lp-exit:
83+
type: int
84+
required: true
85+
description:
86+
Low-power transition time to High-Speed mode.
87+
88+
dphytim4:
89+
type: array
90+
required: true
91+
description: |
92+
Clock lane pre and post data timing parameter: <TCLKZERO TCLKPRE TCLKPOST TCLKTRL>
93+
94+
dphytim5:
95+
type: array
96+
required: true
97+
description: |
98+
High-Speed data lane timing parameter: <THSZERO THSTRL THSEXIT>

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