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thenguyenyfkartben
thenguyenyf
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kartben
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drivers: mipi_dsi: correct formatting for dsi_renesas_ra
Remove redundant code. Format source code to make it prettier. Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
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‎drivers/mipi_dsi/dsi_renesas_ra.c

Lines changed: 68 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -6,17 +6,12 @@
66

77
#define DT_DRV_COMPAT renesas_ra_mipi_dsi
88

9-
#include <zephyr/device.h>
10-
#include <zephyr/devicetree.h>
11-
#include <zephyr/drivers/clock_control.h>
9+
#include <soc.h>
10+
#include <zephyr/kernel.h>
11+
#include <zephyr/logging/log.h>
1212
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
13-
#include <zephyr/drivers/gpio.h>
1413
#include <zephyr/drivers/mipi_dsi.h>
15-
#include <zephyr/drivers/reset.h>
16-
#include <zephyr/irq.h>
17-
#include <zephyr/logging/log.h>
1814
#include "r_mipi_dsi.h"
19-
#include "r_mipi_phy.h"
2015

2116
LOG_MODULE_REGISTER(dsi_renesas_ra, CONFIG_MIPI_DSI_LOG_LEVEL);
2217

@@ -41,6 +36,7 @@ LOG_MODULE_REGISTER(dsi_renesas_ra, CONFIG_MIPI_DSI_LOG_LEVEL);
4136
#define PLL_MUL_SETTING (49)
4237
#define VIDEO_MODE_DELAY (186)
4338
#define ULPS_WAKEUP_PERIOD (97)
39+
4440
struct mipi_dsi_renesas_ra_config {
4541
const struct device *clock_dev;
4642
struct clock_control_ra_subsys_cfg clock_dsi_subsys;
@@ -55,15 +51,6 @@ struct mipi_dsi_renesas_ra_data {
5551
};
5652

5753
void mipi_dsi_seq0(void);
58-
void mipi_dsi_ferr(void);
59-
void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args);
60-
61-
typedef struct {
62-
unsigned char size;
63-
unsigned char buffer[256];
64-
mipi_dsi_cmd_id_t cmd_id;
65-
mipi_dsi_cmd_flag_t flags;
66-
} lcd_table_setting_t;
6754

6855
void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args)
6956
{
@@ -81,7 +68,7 @@ static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
8168
{
8269
struct mipi_dsi_renesas_ra_data *data = dev->data;
8370
mipi_dsi_cfg_t cfg = data->mipi_dsi_cfg;
84-
int ret;
71+
fsp_err_t err;
8572

8673
if (!(mdev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
8774
LOG_ERR("DSI host supports video mode only!");
@@ -95,11 +82,15 @@ static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
9582

9683
cfg.virtual_channel_id = channel;
9784
cfg.num_lanes = mdev->data_lanes;
85+
9886
if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB888) {
9987
cfg.data_type = MIPI_DSI_VIDEO_DATA_24RGB_PIXEL_STREAM;
10088
} else if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB565) {
10189
cfg.data_type = MIPI_DSI_VIDEO_DATA_16RGB_PIXEL_STREAM;
90+
} else {
91+
return -ENOTSUP;
10292
}
93+
10394
cfg.horizontal_active_lines = mdev->timings.hactive;
10495
cfg.horizontal_front_porch = mdev->timings.hfp;
10596
cfg.horizontal_back_porch = mdev->timings.hbp;
@@ -110,15 +101,15 @@ static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
110101
cfg.vertical_back_porch = mdev->timings.vbp;
111102
cfg.vertical_sync_lines = mdev->timings.vsync;
112103

113-
ret = R_MIPI_DSI_Open(&data->mipi_dsi_ctrl, &cfg);
114-
if (ret) {
115-
LOG_ERR("Open DSI failed (%d)", ret);
104+
err = R_MIPI_DSI_Open(&data->mipi_dsi_ctrl, &cfg);
105+
if (err != FSP_SUCCESS) {
106+
LOG_ERR("Open DSI failed (%d)", err);
116107
return -EIO;
117108
}
118109

119-
ret = R_MIPI_DSI_Start(&data->mipi_dsi_ctrl);
120-
if (ret) {
121-
LOG_ERR("Start DSI host failed! (%d)", ret);
110+
err = R_MIPI_DSI_Start(&data->mipi_dsi_ctrl);
111+
if (err != FSP_SUCCESS) {
112+
LOG_ERR("Start DSI host failed! (%d)", err);
122113
return -EIO;
123114
}
124115

@@ -243,41 +234,30 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
243234

244235
ret = clock_control_on(config->clock_dev,
245236
(clock_control_subsys_t)&config->clock_dsi_subsys);
246-
if (ret) {
237+
if (ret != 0) {
247238
LOG_ERR("Enable DSI peripheral clock failed! (%d)", ret);
248239
return ret;
249240
}
250241

251242
k_sem_init(&data->in_transmission, 0, 1);
252243

253244
config->irq_configure();
254-
data->mipi_dsi_cfg.p_context = dev;
255245

256246
return 0;
257247
}
258248

259-
#define IRQ_CONFIGURE_FUNC(id) \
249+
#define RENESAS_MIPI_DSI_DEVICE(id) \
260250
static void mipi_dsi_ra_configure_func_##id(void) \
261251
{ \
262252
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, sq0, irq)] = \
263253
BSP_PRV_IELS_ENUM(EVENT_MIPIDSI_SEQ0); \
264254
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, sq0, irq), \
265-
DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0, \
266-
DEVICE_DT_INST_GET(id), 0); \
255+
DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0, NULL, 0); \
267256
irq_enable(DT_INST_IRQ_BY_NAME(id, sq0, irq)); \
268-
R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, ferr, irq)] = \
269-
BSP_PRV_IELS_ENUM(EVENT_MIPIDSI_FERR); \
270-
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, ferr, irq), \
271-
DT_INST_IRQ_BY_NAME(id, ferr, priority), mipi_dsi_ferr, \
272-
DEVICE_DT_INST_GET(id), 0); \
273-
irq_enable(DT_INST_IRQ_BY_NAME(id, ferr, irq)); \
274-
}
275-
276-
#define IRQ_CONFIGURE_DEFINE(id) .irq_configure = mipi_dsi_ra_configure_func_##id
277-
278-
#define RENESAS_MIPI_DSI_DEVICE(id) \
279-
IRQ_CONFIGURE_FUNC(id) \
257+
} \
258+
\
280259
mipi_phy_ctrl_t mipi_phy_##id##_ctrl; \
260+
\
281261
static const mipi_phy_timing_t mipi_phy_##id##_timing = { \
282262
.t_init = 0x3FFFF & (uint32_t)MIPI_PHY_TINIT, \
283263
.t_clk_prep = (uint8_t)MIPI_PHY_TCLKPREP, \
@@ -291,16 +271,19 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
291271
.dphytim5_b.t_hs_zero = (uint32_t)MIPI_PHY_THSZERO, \
292272
.t_lp_exit = (uint32_t)MIPI_PHY_TLPEXIT, \
293273
}; \
274+
\
294275
static const mipi_phy_cfg_t mipi_phy_##id##_cfg = { \
295276
.pll_settings = {.div = 0, .mul_int = PLL_MUL_SETTING, .mul_frac = 0}, \
296277
.lp_divisor = LP_DIVISOR, \
297278
.p_timing = &mipi_phy_##id##_timing, \
298279
}; \
280+
\
299281
static const mipi_phy_instance_t mipi_phy##id = { \
300282
.p_ctrl = &mipi_phy_##id##_ctrl, \
301283
.p_cfg = &mipi_phy_##id##_cfg, \
302284
.p_api = &g_mipi_phy, \
303285
}; \
286+
\
304287
static const mipi_dsi_extended_cfg_t mipi_dsi_##id##_extended_cfg = { \
305288
.dsi_seq0.ipl = DT_INST_IRQ_BY_NAME(id, sq0, priority), \
306289
.dsi_seq0.irq = DT_INST_IRQ_BY_NAME(id, sq0, irq), \
@@ -323,69 +306,71 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
323306
R_DSILINK_RXIER_CRCERR_Msk | R_DSILINK_RXIER_IBERR_Msk | \
324307
R_DSILINK_RXIER_RXOVFERR_Msk | R_DSILINK_RXIER_PRTOERR_Msk | \
325308
R_DSILINK_RXIER_NORESERR_Msk | R_DSILINK_RXIER_RSIZEERR_Msk | \
326-
R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk | 0x0, \
309+
R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk, \
327310
.dsi_ferrie = R_DSILINK_FERRIER_HTXTO_Msk | R_DSILINK_FERRIER_LRXHTO_Msk | \
328311
R_DSILINK_FERRIER_TATO_Msk | R_DSILINK_FERRIER_ESCENT_Msk | \
329312
R_DSILINK_FERRIER_SYNCESC_Msk | R_DSILINK_FERRIER_CTRL_Msk | \
330-
R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk | 0x0, \
331-
.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk | 0x0, \
332-
.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk | 0x0, \
313+
R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk, \
314+
.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk, \
315+
.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk, \
333316
.dsi_sqch0ie = R_DSILINK_SQCH0IER_AACTFIN_Msk | R_DSILINK_SQCH0IER_ADESFIN_Msk | \
334317
R_DSILINK_SQCH0IER_TXIBERR_Msk | R_DSILINK_SQCH0IER_RXFERR_Msk | \
335318
R_DSILINK_SQCH0IER_RXFAIL_Msk | R_DSILINK_SQCH0IER_RXPFAIL_Msk | \
336-
R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk | \
337-
0x0, \
319+
R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk, \
338320
.dsi_sqch1ie = R_DSILINK_SQCH1IER_AACTFIN_Msk | R_DSILINK_SQCH1IER_ADESFIN_Msk | \
339321
R_DSILINK_SQCH1IER_SIZEERR_Msk | R_DSILINK_SQCH1IER_TXIBERR_Msk | \
340322
R_DSILINK_SQCH1IER_RXFERR_Msk | R_DSILINK_SQCH1IER_RXFAIL_Msk | \
341323
R_DSILINK_SQCH1IER_RXPFAIL_Msk | R_DSILINK_SQCH1IER_RXCORERR_Msk | \
342-
R_DSILINK_SQCH1IER_RXAKE_Msk | 0x0, \
324+
R_DSILINK_SQCH1IER_RXAKE_Msk, \
343325
}; \
326+
\
344327
static const mipi_dsi_timing_t mipi_dsi_##id##_timing = { \
345328
.clock_stop_time = MIPI_PHY_CLKSTPT, \
346329
.clock_beforehand_time = MIPI_PHY_CLKBFHT, \
347330
.clock_keep_time = MIPI_PHY_CLKKPT, \
348331
.go_lp_and_back = MIPI_PHY_GOLPBKT, \
349332
}; \
333+
\
350334
static const struct mipi_dsi_renesas_ra_config ra_config_##id = { \
351335
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
352-
IRQ_CONFIGURE_DEFINE(id), \
353-
.clock_dsi_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp), \
354-
.stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)}}; \
336+
.clock_dsi_subsys = { \
337+
.mstp = DT_INST_CLOCKS_CELL(id, mstp), \
338+
.stop_bit = DT_INST_CLOCKS_CELL(id, stop_bit), \
339+
}, \
340+
.irq_configure = mipi_dsi_ra_configure_func_##id, \
341+
}; \
342+
\
355343
static struct mipi_dsi_renesas_ra_data ra_data_##id = { \
356-
.mipi_dsi_cfg = \
357-
{ \
358-
.p_mipi_phy_instance = &mipi_phy##id, \
359-
.p_timing = &mipi_dsi_##id##_timing, \
360-
.sync_pulse = (0), \
361-
.data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24, \
362-
.vertical_sync_polarity = 1, \
363-
.horizontal_sync_polarity = 1, \
364-
.video_mode_delay = VIDEO_MODE_DELAY, \
365-
.hsa_no_lp = ((0x0) & R_DSILINK_VMSET0R_HSANOLP_Msk), \
366-
.hbp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HBPNOLP_Msk), \
367-
.hfp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HFPNOLP_Msk), \
368-
.num_lanes = \
369-
DT_PROP_BY_IDX(DT_NODELABEL(ili9806e), data_lanes, 0), \
370-
.ulps_wakeup_period = ULPS_WAKEUP_PERIOD, \
371-
.continuous_clock = (1), \
372-
.hs_tx_timeout = 0, \
373-
.lp_rx_timeout = 0, \
374-
.turnaround_timeout = 0, \
375-
.bta_timeout = 0, \
376-
.lprw_timeout = (0 << R_DSILINK_PRESPTOLPSETR_LPRTO_Pos) | 0, \
377-
.hsrw_timeout = (0 << R_DSILINK_PRESPTOHSSETR_HSRTO_Pos) | 0, \
378-
.max_return_packet_size = 1, \
379-
.ecc_enable = (1), \
380-
.crc_check_mask = (mipi_dsi_vc_t)(0x0), \
381-
.scramble_enable = (0), \
382-
.tearing_detect = (0), \
383-
.eotp_enable = (1), \
384-
.p_extend = &mipi_dsi_##id##_extended_cfg, \
385-
.p_callback = mipi_dsi_callback, \
386-
.p_context = NULL, \
387-
}, \
344+
.mipi_dsi_cfg = { \
345+
.p_mipi_phy_instance = &mipi_phy##id, \
346+
.p_timing = &mipi_dsi_##id##_timing, \
347+
.sync_pulse = (0), \
348+
.vertical_sync_polarity = 1, \
349+
.horizontal_sync_polarity = 1, \
350+
.video_mode_delay = VIDEO_MODE_DELAY, \
351+
.hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk, \
352+
.hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk, \
353+
.hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk, \
354+
.ulps_wakeup_period = ULPS_WAKEUP_PERIOD, \
355+
.continuous_clock = (1), \
356+
.hs_tx_timeout = 0, \
357+
.lp_rx_timeout = 0, \
358+
.turnaround_timeout = 0, \
359+
.bta_timeout = 0, \
360+
.lprw_timeout = 0, \
361+
.hsrw_timeout = 0, \
362+
.max_return_packet_size = 1, \
363+
.ecc_enable = (1), \
364+
.crc_check_mask = (mipi_dsi_vc_t)(0x0), \
365+
.scramble_enable = (0), \
366+
.tearing_detect = (0), \
367+
.eotp_enable = (1), \
368+
.p_extend = &mipi_dsi_##id##_extended_cfg, \
369+
.p_callback = mipi_dsi_callback, \
370+
.p_context = DEVICE_DT_INST_GET(id), \
371+
}, \
388372
}; \
373+
\
389374
DEVICE_DT_INST_DEFINE(id, &mipi_dsi_renesas_ra_init, NULL, &ra_data_##id, &ra_config_##id, \
390375
POST_KERNEL, CONFIG_MIPI_DSI_INIT_PRIORITY, &mipi_dsi_api);
391376

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