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| 1 | +.. zephyr:board:: max32650fthr |
| 2 | +
|
| 3 | +Overview |
| 4 | +******** |
| 5 | +The MAX32650FTHR evaluation kit provides a platform for evaluating the capabilities |
| 6 | +of the MAX32650 ultra-low-power memory-scalable microcontroller designed specifically |
| 7 | +for high-performance, battery-powered applications. |
| 8 | + |
| 9 | +The Zephyr port is running on the MAX32650 MCU. |
| 10 | + |
| 11 | +.. image:: img/max32650fthr.webp |
| 12 | + :align: center |
| 13 | + :alt: MAX32650 FTHR Front |
| 14 | + |
| 15 | +Hardware |
| 16 | +******** |
| 17 | + |
| 18 | +- MAX32650 MCU: |
| 19 | + |
| 20 | + - Ultra Efficient Microcontroller for Battery-Powered Applications |
| 21 | + |
| 22 | + - 120MHz Arm Cortex-M4 with FPU |
| 23 | + - SmartDMA Provides Background Memory Transfers with Programmable Data Processing |
| 24 | + - 120MHz High-Speed and 50MHz Low-Power Oscillators |
| 25 | + - 7.3728MHz Low Power Oscillators |
| 26 | + - 32.768kHz and RTC Clock (Requires External Crystal) |
| 27 | + - 8kHz, Always-on, Ultra-Low-Power Oscillator |
| 28 | + - 3MB Internal Flash, 1MB Internal SRAM |
| 29 | + - 104µW/MHz Executing from Cache at 1.1V |
| 30 | + - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup |
| 31 | + - 1.8V and 3.3V I/O with No Level Translators |
| 32 | + - Programming and Debugging |
| 33 | + |
| 34 | + - Scalable Cached External Memory Interfaces |
| 35 | + |
| 36 | + - 120MB/s HyperBus/Xccela DDR Interface |
| 37 | + - SPIXF/SPIXR for External Flash/RAM Expansion |
| 38 | + - 240Mbps SDHC/eMMC/SDIO/microSD Interface |
| 39 | + |
| 40 | + - Optimal Peripheral Mix Provides Platform Scalability |
| 41 | + |
| 42 | + - 16-Channel DMA |
| 43 | + - Three SPI Master (60MHz)/Slave (48MHz) |
| 44 | + - One QuadSPI Master (60MHz)/Slave (48MHz) |
| 45 | + - Up to Three 4Mbaud UARTs with Flow Control |
| 46 | + - Two 1MHz I2C Master/Slave |
| 47 | + - I2S Slave |
| 48 | + - Four-Channel, 7.8ksps, 10-bit Delta-Sigma ADC |
| 49 | + - USB 2.0 Hi-Speed Device Interface with PHY |
| 50 | + - 16 Pulse Train Generators |
| 51 | + - Six 32-bit Timers with 8mA Hi-Drive |
| 52 | + - 1-Wire® Master |
| 53 | + |
| 54 | + - Trust Protection Unit (TPU) for IP/Data and Security |
| 55 | + |
| 56 | + - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) |
| 57 | + - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 |
| 58 | + - Memory Decryption Integrity Unit, Secure Boot ROM |
| 59 | + |
| 60 | +- External devices connected to the MAX32650FTHR: |
| 61 | + |
| 62 | + - Battery Connector and Charging Circuit |
| 63 | + - Micro-SD Card Interface |
| 64 | + - USB 2.0 Full-Speed Device Interface |
| 65 | + - MAX11261 6-Channel, 24-Bit, 16ksps, ADC |
| 66 | + - Adafruit® Feather Board Compatible |
| 67 | + |
| 68 | +Supported Features |
| 69 | +================== |
| 70 | + |
| 71 | +The ``max32650fthr`` board supports the following interfaces: |
| 72 | + |
| 73 | ++-----------+------------+-------------------------------------+ |
| 74 | +| Interface | Controller | Driver/Component | |
| 75 | ++===========+============+=====================================+ |
| 76 | +| NVIC | on-chip | nested vector interrupt controller | |
| 77 | ++-----------+------------+-------------------------------------+ |
| 78 | +| SYSTICK | on-chip | systick | |
| 79 | ++-----------+------------+-------------------------------------+ |
| 80 | +| CLOCK | on-chip | clock and reset control | |
| 81 | ++-----------+------------+-------------------------------------+ |
| 82 | +| GPIO | on-chip | gpio | |
| 83 | ++-----------+------------+-------------------------------------+ |
| 84 | +| UART | on-chip | serial | |
| 85 | ++-----------+------------+-------------------------------------+ |
| 86 | + |
| 87 | +Programming and Debugging |
| 88 | +************************* |
| 89 | + |
| 90 | +Flashing |
| 91 | +======== |
| 92 | +The MAX32650 MCU can be flashed by connecting an external debug probe to the |
| 93 | +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J5. |
| 94 | +Logic levels are fixed to VDDIO (1.8V). |
| 95 | + |
| 96 | +Once the debug probe is connected to your host computer, then you can simply run the |
| 97 | +``west flash`` command to write a firmware image into flash. |
| 98 | + |
| 99 | +.. note:: |
| 100 | + |
| 101 | + This board uses OpenOCD as the default debug interface. You can also use |
| 102 | + a Segger J-Link with Segger's native tooling by overriding the runner, |
| 103 | + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should |
| 104 | + be connected to the standard 2*5 pin debug connector (J5) using an |
| 105 | + appropriate adapter board and cable |
| 106 | + |
| 107 | +Debugging |
| 108 | +========= |
| 109 | +Please refer to the `Flashing`_ section and run the ``west debug`` command |
| 110 | +instead of ``west flash``. |
| 111 | + |
| 112 | +References |
| 113 | +********** |
| 114 | + |
| 115 | +- `MAX32650FTHR web page`_ |
| 116 | + |
| 117 | +.. _MAX32650FTHR web page: |
| 118 | + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html |
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