soc: cva6: Implement missing cache management APIs

In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

Author: WorldofJARcraft

soc/openhwgroup/cva6/CMakeLists.txt

@@ -3,6 +3,6 @@
 
 add_subdirectory(${SOC_SERIES})
 
-zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT soc_cache_management.c)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/openhwgroup/cva6/Kconfig

@@ -3,9 +3,6 @@
 
 if SOC_FAMILY_OPENHWGROUP_CVA6
 
-config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS
-	bool "Include non-standard cache management operations (currently global cache disable)"
-
 rsource "*/Kconfig"
 
 endif # SOC_FAMILY_OPENHWGROUP_CVA6

soc/openhwgroup/cva6/soc_cache_management.c

@@ -21,6 +21,49 @@ void __weak arch_dcache_disable(void)
 	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
 }
 
+int __weak arch_dcache_flush_all(void)
+{
+	arch_dcache_disable();
+	arch_dcache_enable();
+
+	return 0;
+}
+
+int __weak arch_dcache_invd_all(void)
+{
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_flush_and_invd_all(void)
+{
+	return arch_dcache_flush_all();
+}
+
+/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
+int __weak arch_dcache_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
 void __weak arch_icache_enable(void)
 {
 	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
@@ -31,6 +74,49 @@ void __weak arch_icache_disable(void)
 	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
 }
 
+int __weak arch_icache_flush_all(void)
+{
+	arch_icache_disable();
+	arch_icache_enable();
+
+	return 0;
+}
+
+int __weak arch_icache_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_flush_and_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
+int __weak arch_icache_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
 /* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */
 /* this prevents a linker error when the function is not defined */
 void __weak arch_cache_init(void)