soc: cva6: Add device tree node for RISC-V mtimer

The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

Author: WorldofJARcraft

boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts

@@ -30,6 +30,10 @@
 	status = "okay";
 };
 
+&mtimer {
+	status = "okay";
+};
+
 &eth {
 	local-mac-address = [00 18 3e 02 e3 7f];
 	status = "okay";

boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts

@@ -26,7 +26,11 @@
 	status = "okay";
 };
 
-&clint{
+&clint {
+	status = "okay";
+};
+
+&mtimer {
 	status = "okay";
 };
 

dts/riscv/openhwgroup/cva6.dtsi

@@ -93,6 +93,14 @@
 			status = "disabled";
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			status = "disabled";
+		};
+
 		/*
 		 * Xilinx AXI DMA.
 		 * Part of the Xilinx AXI Ethernet Subsystem.