dts: bindings: remove legacy MDIO-related properties/defines

Remove any properties from the Xilinx GEM DT node specification
and the associated header in dt-bindings that relate to the
legacy MDIO/PHY support.

Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>

Author: ibirnbaum

dts/bindings/ethernet/xlnx,gem.yaml

@@ -28,66 +28,6 @@ properties:
       item must be set to the clock frequency of the PLL supplying the
       respective GEM's TX clock - by default, this is the IO PLL.
 
-  mdc-divider:
-    type: int
-    required: true
-    description: |
-      The MDC clock divider for the respective GEM. This is the divider
-      applied to the LPD_LSBUS clock in order to derive MDIO interface
-      clock driving communications with the attached PHY. Refer to the
-      ZynqMP register documentation (ug1087), network_config (GEM) Register
-      Description, bits [20:18] to determine the appropriate divider for
-      the current target's LPD LSBUS clock frequency.
-
-  init-mdio-phy:
-    type: boolean
-    description: |
-      Activates the management of a PHY associated with the controller in-
-      stance. If this parameter is activated at the board level, the de-
-      fault values of the associated parameters mdio-phy-address, phy-poll-
-      interval, link-speed and advertise-lower-link-speeds should be checked
-      and overwritten at the board level if required.
-
-  mdio-phy-address:
-    type: int
-    required: true
-    description: |
-      The address on the MDIO bus of the PHY associated with the controller
-      instance. Set the address to 0 for auto-detection (first responding
-      PHY will be claimed by the driver, watch out in case of shared MDIO
-      use), or to a fixed address between 1 and 32.
-
-  phy-poll-interval:
-    type: int
-    required: true
-    description: |
-      PHY status polling interval in milliseconds for a driver instance
-      managing an associated PHY.
-
-  link-speed:
-    type: int
-    required: true
-    description: |
-      Nominal link speed. If no PHY is managed by an instance of this driver,
-      the respective controller will be configured to match the link speed
-      specified here. If a PHY is managed by the driver, advertisement of
-      the link speed specified here will be requested. If the optional pro-
-      perty advertise-lower-link-speeds is set, advertisement of the link
-      speed specified here plus any valid link speed below this value will
-      be requested.
-    enum:
-      - 1
-      - 2
-      - 3
-
-  advertise-lower-link-speeds:
-    type: boolean
-    description: |
-      Indicates to a driver instance which manages an associated PHY on
-      the MDIO bus to include link speeds lower than the nominal value
-      set in the link-speed property in the advertisement when requesting
-      link speed auto-negotiation with a peer system.
-
   handle-rx-in-isr:
     type: boolean
     description: |
@@ -318,11 +258,6 @@ properties:
     description: Optional feature flag - Discard non-VLAN frames. When set,
       only VLAN tagged frames will be passed to the address matching logic.
 
-  full-duplex:
-    type: boolean
-    description: |
-      Optional feature flag - Enables full duplex reception and transmission.
-
   discard-rx-frame-ahb-unavail:
     type: boolean
     description: |

include/zephyr/dt-bindings/ethernet/xlnx_gem.h

@@ -6,39 +6,6 @@
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
 
-/* PHY auto-detection alias */
-#define XLNX_GEM_PHY_AUTO_DETECT 0
-
-/*
- * MDC divider values
- *
- * According to the ZynqMP's gem.network_config register documentation (UG1087),
- * divider /32 is the reset value. The network_config[mdc_clock_division]
- * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
- * as it claims that the MDC clock division is applied to the cpu_1x clock
- * which the UltraScale doesn't have. Contradicting information is provided in
- * the UltraScale TRM (UG1085), which mentions in chapter 34, section "Configure
- * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
- * Xilinx's emacps driver doesn't (or no longer does) limit the range of dividers
- * on the UltraScale compared to the Zynq-7000.
- * -> Contrary to earlier revisions of this driver, all dividers are available
- *    to both the UltraScale and the Zynq-7000.
- */
-
-#define XLNX_GEM_MDC_DIVIDER_8   0 /* cpu_1x or IOU_SWITCH_CLK     <  20 MHz */
-#define XLNX_GEM_MDC_DIVIDER_16  1 /* cpu_1x or IOU_SWITCH_CLK  20 -  40 MHz */
-#define XLNX_GEM_MDC_DIVIDER_32  2 /* cpu_1x or IOU_SWITCH_CLK  40 -  80 MHz */
-#define XLNX_GEM_MDC_DIVIDER_48  3 /* cpu_1x or IOU_SWITCH_CLK  80 - 120 MHz */
-#define XLNX_GEM_MDC_DIVIDER_64  4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
-#define XLNX_GEM_MDC_DIVIDER_96  5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
-#define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
-#define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
-
-/* Link speed values */
-#define XLNX_GEM_LINK_SPEED_10MBIT  1
-#define XLNX_GEM_LINK_SPEED_100MBIT 2
-#define XLNX_GEM_LINK_SPEED_1GBIT   3
-
 /* AMBA AHB data bus width */
 #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT  0
 #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_64BIT  1