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soc: microchip: add new soc sama7d65
Product URL: https://www.microchip.com/en-us/product/SAMA7D65 Signed-off-by: Tony Han <tony.han@microchip.com>
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‎soc/microchip/sam/Kconfig

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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_SAMA7D6
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select ARM
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select CPU_CORTEX_A7
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select SOC_EARLY_INIT_HOOK
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config SOC_SERIES_SAMA7G5
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select ARM
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select CPU_CORTEX_A7

‎soc/microchip/sam/sama7d6/CMakeLists.txt

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# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(soc.c)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

‎soc/microchip/sam/sama7d6/Kconfig.defconfig

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# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_SAMA7D6
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config NUM_IRQS
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default 189
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/soc/timer@e1800000,clock-frequency)
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config MMU
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default y
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endif # SOC_SERIES_SAMA7D6

‎soc/microchip/sam/sama7d6/Kconfig.soc

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# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_SAMA7D6
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bool
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select SOC_FAMILY_MICROCHIP_SAM
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help
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Enable support for Microchip SAM Microprocessors.
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config SOC_SERIES
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default "sama7d6" if SOC_SERIES_SAMA7D6
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rsource "Kconfig.soc.sam*"

‎soc/microchip/sam/sama7d6/Kconfig.soc.sama7d65

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# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SAMA7D65
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bool
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select SOC_SERIES_SAMA7D6
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config SOC
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default "sama7d65" if SOC_SAMA7D65

‎soc/microchip/sam/sama7d6/soc.c

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/*
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* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <zephyr/init.h>
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#include <zephyr/arch/arm/mmu/arm_mmu.h>
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#include <zephyr/kernel.h>
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#define MMU_REGION_FLEXCOM_DEFN(idx, n) \
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COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flx##n)), \
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(MMU_REGION_FLAT_ENTRY("flexcom"#n, FLEXCOM##n##_BASE_ADDRESS, 0x4000, \
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),), \
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())
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("vectors", CONFIG_KERNEL_VM_BASE, 0x1000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
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FOR_EACH_IDX(MMU_REGION_FLEXCOM_DEFN, (), 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10)
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MMU_REGION_FLAT_ENTRY("gic", GIC_DISTRIBUTOR_BASE, 0x1100,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("pioa", PIO_BASE_ADDRESS, 0x4000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("pit64b0", PIT64B0_BASE_ADDRESS, 0x4000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("pmc", PMC_BASE_ADDRESS, 0x200,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("sckc", SCKC_BASE_ADDRESS, 0x4,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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void relocate_vector_table(void)
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{
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write_vbar(CONFIG_KERNEL_VM_BASE);
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}
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void soc_early_init_hook(void)
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{
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/* Enable Generic clock for PIT64B0 for system tick */
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PMC_REGS->PMC_PCR = PMC_PCR_CMD(1) | PMC_PCR_GCLKEN(1) | PMC_PCR_EN(1) |
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PMC_PCR_GCLKDIV(20 - 1) | PMC_PCR_GCLKCSS_MCK1 |
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PMC_PCR_PID(ID_PIT64B0);
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}

‎soc/microchip/sam/sama7d6/soc.h

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/*
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* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SAMA7D6_SOC__H_
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#define __SAMA7D6_SOC__H_
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#ifdef CONFIG_SOC_SAMA7D65
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#define __SAMA7D65__
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#endif
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#include "sam.h"
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/* number of clocks registered */
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#define SOC_NUM_CLOCK_PLL_FRAC 9
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#define SOC_NUM_CLOCK_PLL_DIV (SOC_NUM_CLOCK_PLL_FRAC + 1) /* AUDIO PLL: DIVPMC, DIVIO */
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#define SOC_NUM_CLOCK_MASTER 10 /* MCK 0 ~ 9 */
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#define SOC_NUM_CLOCK_PROGRAMMABLE 8 /* MCK 0 ~ 7 */
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#define SOC_NUM_CLOCK_SYSTEM 8 /* PCK 0 ~ 7 */
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#define SOC_NUM_CLOCK_PERIPHERAL 72
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#define SOC_NUM_CLOCK_GENERATED 44
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#endif /* __SAMA7D6_SOC__H_ */

‎soc/microchip/sam/soc.yml

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family:
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- name: microchip_sam
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series:
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- name: sama7d6
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socs:
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- name: sama7d65
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- name: sama7g5
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socs:
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- name: sama7g54

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