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samples: Add BL54L15/L15u DVK support
Adds support for the BL54L15 and BL54L15u DVK boards. Signed-off-by: Greg Leach <greg.leach@ezurio.com>
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‎samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&uart20 {
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compatible = "nordic,nrf-uarte";
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current-speed = <1000000>;
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status = "okay";
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hw-flow-control;
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};

‎samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp_df.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&uart20 {
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compatible = "nordic,nrf-uarte";
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current-speed = <1000000>;
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status = "okay";
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hw-flow-control;
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};
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&radio {
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status = "okay";
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/* This is an example number of antennas that may be available
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* on antenna matrix board.
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*/
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dfe-antenna-num = <10>;
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/* This is an example switch pattern that will be used to set an
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* antenna for Tx PDU (period before start of Tx CTE).
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*/
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dfe-pdu-antenna = <0x0>;
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/* These are example GPIO pin numbers that are provided to
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* Radio peripheral. The pins will be acquired by Radio to
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* drive antenna switching when AoD is enabled.
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*/
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dfegpio0-gpios = <&gpio1 4 0>;
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dfegpio1-gpios = <&gpio1 5 0>;
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dfegpio2-gpios = <&gpio1 6 0>;
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dfegpio3-gpios = <&gpio1 7 0>;
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};

‎samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&uart20 {
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compatible = "nordic,nrf-uarte";
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current-speed = <1000000>;
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status = "okay";
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hw-flow-control;
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};

‎samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp_df.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&uart20 {
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compatible = "nordic,nrf-uarte";
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current-speed = <1000000>;
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status = "okay";
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hw-flow-control;
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};
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&radio {
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status = "okay";
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/* This is an example number of antennas that may be available
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* on antenna matrix board.
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*/
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dfe-antenna-num = <10>;
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/* This is an example switch pattern that will be used to set an
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* antenna for Tx PDU (period before start of Tx CTE).
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*/
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dfe-pdu-antenna = <0x0>;
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/* These are example GPIO pin numbers that are provided to
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* Radio peripheral. The pins will be acquired by Radio to
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* drive antenna switching when AoD is enabled.
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*/
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dfegpio0-gpios = <&gpio1 4 0>;
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dfegpio1-gpios = <&gpio1 5 0>;
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dfegpio2-gpios = <&gpio1 6 0>;
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dfegpio3-gpios = <&gpio1 7 0>;
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};

‎samples/drivers/adc/adc_dt/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*/
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/ {
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zephyr,user {
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
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};
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};
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&adc {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
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zephyr,resolution = <10>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_VDD>;
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@7 {
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reg = <7>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
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zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/adc/adc_dt/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*/
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/ {
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zephyr,user {
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
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};
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};
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&adc {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
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zephyr,resolution = <10>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_VDD>;
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@7 {
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reg = <7>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
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zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/adc/adc_sequence/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*/
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/ {
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zephyr,user {
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
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};
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};
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/ {
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aliases {
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adc0 = &adc;
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};
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};
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&adc {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
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zephyr,resolution = <10>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_DVDD>; /* 0.9 V internal */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@7 {
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reg = <7>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
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zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/adc/adc_sequence/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay

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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*/
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/ {
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zephyr,user {
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
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};
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};
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/ {
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aliases {
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adc0 = &adc;
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};
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};
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&adc {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
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zephyr,resolution = <10>;
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};
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channel@1 {
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reg = <1>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@2 {
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reg = <2>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_DVDD>; /* 0.9 V internal */
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zephyr,resolution = <12>;
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zephyr,oversampling = <8>;
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};
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channel@7 {
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reg = <7>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
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zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
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zephyr,resolution = <12>;
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};
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};

‎samples/drivers/audio/dmic/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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pdm20_default_alt: pdm20_default_alt {
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group1 {
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psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
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<NRF_PSEL(PDM_DIN, 1, 13)>;
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};
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};
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};
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dmic_dev: &pdm20 {
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status = "okay";
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pinctrl-0 = <&pdm20_default_alt>;
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pinctrl-names = "default";
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clock-source = "PCLK32M";
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};

‎samples/drivers/audio/dmic/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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pdm20_default_alt: pdm20_default_alt {
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group1 {
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psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
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<NRF_PSEL(PDM_DIN, 1, 13)>;
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};
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};
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};
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dmic_dev: &pdm20 {
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status = "okay";
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pinctrl-0 = <&pdm20_default_alt>;
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pinctrl-names = "default";
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clock-source = "PCLK32M";
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};

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