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boards: ezurio: bl54l15_dvk: Add BL54L15/L15u DVK support
Adds support for the BL54L15 and BL54L15u DVK boards. Signed-off-by: Greg Leach <greg.leach@ezurio.com>
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‎boards/ezurio/bl54l15_dvk/Kconfig

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# Copyright (c) 2025 Ezurio LLC
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# SPDX-License-Identifier: Apache-2.0
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# BL54L15 DVK board configuration
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if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
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DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
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config NRF_TRUSTZONE_FLASH_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the flash region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral-specific symbols.
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config NRF_TRUSTZONE_RAM_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the RAM region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral specific symbols.
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endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS

‎boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2025 Ezurio LLC
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_BL54L15_DVK
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select SOC_NRF54L10_CPUAPP if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS
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select SOC_NRF54L15_CPUAPP if BOARD_BL54L15_DVK_NRF54L15_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
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select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15_DVK_NRF54L15_CPUFLPR || \
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BOARD_BL54L15_DVK_NRF54L15_CPUFLPR_XIP

‎boards/ezurio/bl54l15_dvk/Kconfig.defconfig

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2025 Ezurio LLC
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# SPDX-License-Identifier: Apache-2.0
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
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DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
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if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
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if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
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config BT_CTLR
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default BT
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config FLASH_LOAD_OFFSET
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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config FLASH_LOAD_SIZE
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default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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# By default, if we build for a Non-Secure version of the board,
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# enable building with TF-M as the Secure Execution Environment.
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config BUILD_WITH_TFM
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default y
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endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS

‎boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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led0: led_0 {
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gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
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label = "Green LED 0";
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};
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led1: led_1 {
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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label = "Green LED 1";
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};
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led2: led_2 {
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gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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label = "Green LED 2";
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};
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led3: led_3 {
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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label = "Green LED 3";
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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/*
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* PWM signal can be exposed on GPIO pin only within same domain.
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* There is only one domain which contains both PWM and GPIO:
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* PWM20/21/22 and GPIO Port P1.
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* Only LEDs connected to P1 can work with PWM, for example LED1.
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*/
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pwm_led1: pwm_led_1 {
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pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
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};
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};
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buttons {
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compatible = "gpio-keys";
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button0: button_0 {
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gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 0";
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zephyr,code = <INPUT_KEY_0>;
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};
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button1: button_1 {
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gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 1";
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zephyr,code = <INPUT_KEY_1>;
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};
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button2: button_2 {
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gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 2";
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zephyr,code = <INPUT_KEY_2>;
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};
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button3: button_3 {
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gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
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label = "Push button 3";
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zephyr,code = <INPUT_KEY_3>;
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};
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};
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aliases {
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led0 = &led0;
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led1 = &led1;
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led2 = &led2;
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led3 = &led3;
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pwm-led0 = &pwm_led1;
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sw0 = &button0;
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sw1 = &button1;
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sw2 = &button2;
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sw3 = &button3;
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watchdog0 = &wdt31;
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};
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};
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&uart20 {
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current-speed = <115200>;
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pinctrl-0 = <&uart20_default>;
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pinctrl-1 = <&uart20_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&uart30 {
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current-speed = <115200>;
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pinctrl-0 = <&uart30_default>;
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pinctrl-1 = <&uart30_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&pwm20 {
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status = "okay";
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pinctrl-0 = <&pwm20_default>;
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pinctrl-1 = <&pwm20_sleep>;
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pinctrl-names = "default", "sleep";
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};
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/* Get a node label for wi-fi spi to use in shield files */
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wifi_spi: &spi22 {};

‎boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* Copyright (c) 2025 Ezurio LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf54l10_cpuapp.dtsi>
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#include "nrf54l_10_15_cpuapp_common.dtsi"
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/ {
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compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp";
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model = "Ezurio BL54L15 DVK nRF54L10 Application MCU";
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &cpuapp_sram;
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};
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};
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/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(192)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
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};
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(1022)>;
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};
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/* These partition sizes assume no FLPR area in RRAM */
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(224)>;
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};
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slot0_ns_partition: partition@48000 {
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label = "image-0-nonsecure";
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reg = <0x48000 DT_SIZE_K(224)>;
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};
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slot1_partition: partition@80000 {
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label = "image-1";
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reg = <0x80000 DT_SIZE_K(224)>;
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};
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slot1_ns_partition: partition@b8000 {
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label = "image-1-nonsecure";
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reg = <0xb8000 DT_SIZE_K(224)>;
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};
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/* 32K from 0xf0000 to 0xf7fff reserved for TF-M partitions */
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storage_partition: partition@f8000 {
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label = "storage";
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reg = <0xf8000 DT_SIZE_K(28)>;
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};
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/* 2K from 0xff000 to 0xff7ff unused */
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};
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};

‎boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2025 Ezurio LLC
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# SPDX-License-Identifier: Apache-2.0
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identifier: bl54l15_dvk/nrf54l10/cpuapp
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name: BL54L15-DVK-nRF54L10-Application
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- zephyr
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sysbuild: true
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ram: 192
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flash: 230
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supported:
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- adc
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- counter
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- gpio
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- i2c
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- pwm
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- retained_mem
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- spi
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- watchdog
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- i2s

‎boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2025 Ezurio LLC
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# SPDX-License-Identifier: Apache-2.0
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y

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